Self-aligned mask to reduce cell layout area

Details Self-aligned mask to reduce cell layout area Self-aligned mask to reduce cell layout area

2005-12-13

2005-12-13

Deo, Duy-Vu N. (Department: 1765)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S700000, C438S719000, C438S723000, C438S724000, C438S690000

Reexamination Certificate

active

06974770

ABSTRACT:
Self-aligning vias and trenches etched between adjacent lines of metallization allows the area of the dielectric substrate allocated to the via or trench to be significantly reduced without increasing the possibility of electrical shorts to the adjacent lines of metallization.

REFERENCES:
patent: 6482689 (2002-11-01), Trivedi
patent: 6803318 (2004-10-01), Qiao et al.
patent: 6806195 (2004-10-01), Enomoto et al.
patent: 6812141 (2004-11-01), Gaidis et al.

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