Self-aligned LDMOS fabrication method integrated...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C257SE21427

Reexamination Certificate

active

07575977

ABSTRACT:
An integrated circuit includes both LDMOS devices and one or more low-power CMOS devices that are concurrently formed on a substrate using a deep sub-micron VLSI fabrication process. The LDMOS polycrystalline silicon (polysilicon) gate structure is patterned using a two-mask etching process. The first etch mask is used to define a first edge of the gate structure located away from the deep body/drain implant. The second etch mask is then used to define a second edge of the gate structure, and the second etch mask is then retained on the gate structure during subsequent formation of the deep body/drain implant. After the deep implant, shallow implants and metallization are formed to complete the LDMOS device.

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Bengtsson et al. “Small-Signal and Power Evaluation of Novel BiCMOS-Compatible Short-Channel LDMOS Technology,” IEEE Transactions on Microwave Theory and Techniques, vol. 51, No. 3, Mar. 2003, pp. 1052- 1056.
Itonaga et al. “A High-Performance and Low-Noise CMOS Image Sensor with an Expanding Photodiode under the Isolation Oxide,” Electron Devices Meeting, 2005, IEDM Technical Digest, IEEE International, Dec. 5-7, 2005, 4 pgs.

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