Self-aligned lateral DMOS with spacer drift region

Details Self-aligned lateral DMOS with spacer drift region Self-aligned lateral DMOS with spacer drift region

1998-05-18

2001-06-26

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S337000, C257S336000, C257S344000

Reexamination Certificate

active

06252278

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to lateral double diffused metal oxide semiconductor (LDMOS) transistors and, in particular, to an improved LDMOS transistor having a drift region separated from the gate by a sidewall spacer.
BACKGROUND OF THE INVENTION
Power semiconductor devices are currently being used in many applications. Such power devices include high voltage integrated circuits which typically include one or more high voltage transistors, often on the same chip as low voltage circuitry. A commonly used high voltage component for these circuits is the lateral double diffused MOS transistor (LDMOS). LDMOS structures used in high voltage integrated circuits may generally be fabricated using some of the same techniques used to fabricate low voltage circuitry. In general, these existing LDMOS structures are fabricated in a thick epitaxial layer of opposite conductivity type to the substrate.
High power applications have called for the use of such LDMOS transistors primarily because they possess lower “on” resistance, faster switching speed, and lower gate drive power dissipation than their bipolar counterparts. One of the major measures of performance for an LDMOS transistor is its on resistance and its breakdown voltage. Clearly, it is preferred to have a low on resistance with a high breakdown voltage. However, since the on resistance is proportional to the epitaxial layer resistivity, higher breakdown voltages must generally be traded off for limited drive current capability. In other words, the breakdown voltage of the LDMOS transistor is optimized by adjusting the drift region, but often at the cost of increased resistivity due to typically lower doped concentrations.
One example of such an LDMOS structure is shown in U.S. Pat. No. 5,517,046 to Hsing et al. In the '046 patent, a lateral DMOS transistor is formed in an N-type silicon epitaxial layer. An N-type enhanced drift region is formed between the drain and gate of the transistor in the N-type epitaxial layer. The N-type enhanced drift region serves to significantly reduce on resistance without significantly reducing breakdown voltage.
Specifically,
FIG. 1
illustrates the prior art LDMOS transistor of the '046 patent. A starting substrate of P-type silicon
20
is provided. An epitaxial layer of N-type
22
is grown on the surface of the substrate using conventional techniques. Optionally, an N
+
buried layer
23
may be formed at the interface of the N
−
epitaxial layer
22
on the substrate. This is provided to reduce the beta of any parasitic PNP bipolar transistor formed. Next, a thin gate oxide layer
24
is formed atop the epitaxial layer
22
. A polysilicon layer is then deposited atop the gate oxide
24
and patterned and etched to form a polysilicon gate
26
. Boron ions are then implanted to form a P
−
type body
29
. Further, a P
+
body contact
28
is then formed in the body
29
using ion implantation.
An N enhanced drift region
31
is then formed using ion implantation. The drift region
31
is self-aligned with the gate
26
. A second implantation process is then used to form N
+
source region
32
and N
+
drain region
34
. Finally, metal source contact
37
and drain contact
38
are then formed by conventional techniques. The breakdown voltage of the transistor is dependent upon the spacing between the drain
34
and the gate
26
and the total charge in the drift region.
Although effective, what is still needed is a LDMOS transistor that exhibits even higher breakdown voltage while maintaining low on resistance.
SUMMARY OF THE INVENTION
An LDMOS transistor formed in an N-type substrate is disclosed. The LDMOS transistor comprises: a polysilicon gate atop said N-type substrate, said polysilicon gate comprising a thin gate oxide layer and a polysilicon layer, said polysilicon gate having a source side and a drain side; a P-type well formed in said N-type substrate extending from said source side to under said polysilicon gate; a N
+
source region formed in said P-type well and adjacent to said polysilicon gate; a N
+
drain region formed in said N-type substrate and in said drain side of said polysilicon gate; and an N-type drift region between said N
+
drain region and said polysilicon gate, wherein said N-type drift region not extending to said polysilicon gate.


REFERENCES:
patent: 4771014 (1988-09-01), Liou et al.
patent: 5204541 (1993-04-01), Smayling et al.
patent: 5304827 (1994-04-01), Malhi et al.
patent: 5369045 (1994-11-01), Ng et al.
patent: 5382536 (1995-01-01), Malhi et al.
patent: 5796146 (1998-08-01), Ludikhuize

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