Self-aligned isolation and planarization process for memory arra

Details Self-aligned isolation and planarization process for memory arra Self-aligned isolation and planarization process for memory arra

1996-06-24

1998-06-09

Dang, Trung

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

436257, 436296, 436297, 436425, H01L 21336

Patent

active

057633096

ABSTRACT:
A self-aligned planarization and isolation technique achieves smaller dimension memory cells using self-aligned isolation trenches. The process involves defining the lines of buried diffusion and first layer of polysilicon using a single mask. A protective oxide is formed between the polysilicon lines. Then a second mask is used with non-critical alignment to select polysilicon lines to define self-aligned etch regions. The trenches are made using a high selectivity etching recipe which etches through polysilicon and the silicon substrate in the selected lines faster than the protective oxide. Thus, a single mask defines the diffusion regions, the first layer of polysilicon, and the isolation trenches. The mask used for selecting polysilicon lines for definition of isolation structures does not need to be critically aligned, removing the alignment tolerance for formation of the isolation structures out of the layout of the array.

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Aritome, et al., "A 0.67.mu.m.sup.2 Self-Aligned Shallow Trench Isolation Cell(SA-STI Cell) For 3V-only 256Mbit NAND EEPROMs," IEDM, pp. 61-64, (1994).
Kato, et al., "A 0.4.mu.m.sup.2 Self-Aligned Contactless Memory Cell Technology Suitable for 256-Mbit Flash Memories," IEDM, pp. 921-923, (1994).

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