Self-aligned inner gate recess channel transistor and method...

Details Self-aligned inner gate recess channel transistor and method... Self-aligned inner gate recess channel transistor and method...

2006-12-26

2006-12-26

Nguyen, Cuong (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S331000, C257S330000, C257S332000

Reexamination Certificate

active

07154144

ABSTRACT:
A self-aligned inner gate recess channel in a semiconductor substrate includes a recess trench formed in an active region of the substrate, a gate dielectric layer formed on a bottom portion of the recess trench, recess inner sidewall spacers formed on sidewalls of the recess trench, a gate formed in the recess trench so that an upper portion of the gate protrudes above an upper surface of the substrate, wherein a thickness of the recess inner sidewall spacers causes a center portion of the gate to have a smaller width than the protruding upper portion and a lower portion of the gate, a gate mask formed on the gate layer, gate sidewall spacers formed on the protruding upper portion of gate and the gate mask, and a source/drain region formed in the active region of the substrate adjacent the gate sidewall spacers.

REFERENCES:
patent: 4536782 (1985-08-01), Brown
patent: 5371024 (1994-12-01), Hieda et al.
patent: 6150219 (2000-11-01), Tung
patent: 6358800 (2002-03-01), Tseng et al.
patent: 6448590 (2002-09-01), Adkisson et al.
patent: 6677209 (2004-01-01), Farrar
patent: 2003-0019581 (2003-03-01), None

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