Self-aligned gate isolation

Details Self-aligned gate isolation Self-aligned gate isolation

2007-05-29

2007-05-29

Lee, Hsien-Ming (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S229000, C438S230000, C438S296000, C438S299000, C257S274000, C257S338000, C257S351000

Reexamination Certificate

active

11196533

ABSTRACT:
Embodiments of the invention include a circuit with a transistor having a self-aligned gate. Insulating isolation structures may be formed, self-aligned to diffusions. The gate may then be formed self-aligned to the insulating isolation structures.

REFERENCES:
patent: 2005/0035427 (2005-02-01), Park et al.
patent: 2005/0179072 (2005-08-01), Rhodes
patent: 2006/0043464 (2006-03-01), Tsunoda et al.
Peter L.D. Chang, “Memory with Split Gate Devices and Method of Fabrication”, U.S. Appl. No. 10/816,282, filed Mar. 31, 2004.
Peter L.D. Chang, “Memory Cell Using Silicon Carbide”, U.S. Appl. No. 10/874,557, filed Jun. 22, 2004.
Brian Doyle et al., “Independently Accessed Double-Gate and Tri-Gate Transistors in Same Process Flow”, U.S. Appl. No. 10/955,670, filed Sep. 29, 2004.
Peter L.D. Chang, “Method for Isolating Semiconductor Device Structures and Structures Thereof”, U.S. Appl. No. 10/956,320, filed Sep. 30, 2004.
Peter L.D. Chang, “Self-Aligned Contacts for Transistors”, U.S. Appl. No. 11/097,429, filed Mar. 31, 2004.
Peter L.D. Chang, “Independently Accessed Double-Gate and Tri-Gate Transistors in Same Process Flow”, U.S. Appl. No. 11/124,572, filed May 4, 2005.

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