Self-aligned gate and method

Details Self-aligned gate and method Self-aligned gate and method

2000-12-07

2004-08-10

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S289000, C438S302000, C438S305000, C438S595000

Reexamination Certificate

active

06774001

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor integrated circuit processing, and more specifically to an improved method for forming features having critical dimensions, such as transistor gates in an integrated circuit.
BACKGROUND OF THE INVENTION
Semiconductor manufacturing is capital intensive and extremely competitive. Survival of semiconductor manufacturing concerns depends on constant innovation to produce more components at lower costs. New device designs often require additional capital investment in order to fabricate the new designs, as is explained below in more detail.
The manufacturing cost of an integrated circuit depends in part on how much semiconductor area is required to implement desired functions. The area, in turn, is defined by geometries and sizes of elements of active components such as FET gates and by diffused or implanted regions such as FET sources and drains and bipolar transistor emitters and bases.
The smallest features in many devices have a critical dimension that is often similar in size to the wavelengths of light used to photolithographically define the feature. As a result, further reduction of the size of the critical dimension may require new equipment, using either shorter light wavelengths or techniques not dependent on light for feature definition (e.g., using focused electron beams). Capital costs of several tens of million dollars each are not unusual for these types of equipment.
Maximum operating frequency is a figure of merit for integrated circuits and is determined by a confluence of factors. Parasitic capacitance in transistors making up the integrated circuits strongly affects maximum operating frequency. Higher operating frequencies also tend to require smaller feature sizes for a variety of reasons. As a result, design techniques that reduce parasitic capacitance or that result in smaller feature sizes can be extremely valuable to semiconductor manufacturers.
SUMMARY OF THE INVENTION
The present invention is directed toward methods of making transistors on integrated circuits and transistors and integrated circuits made using such methods. One method includes forming one or more layers, which may be dielectric layers, on a surface of a semiconductor substrate that includes planar isolation structures that were previously formed on the surface of the semiconductor wafer. Openings having a first width are formed through a top one of the series of layers and a blanket dielectric layer having a predetermined thickness is formed in the openings and on the series of layers. An anisotropic etch removes the blanket dielectric layer from the series of layers and from bottoms of the openings but not from sidewalls of the openings, thereby forming dielectric spacers. As a result, a gap between the dielectric spacers has a second width that is equal to the first width minus twice the thickness of the blanket dielectric layer.
A first ion implantation through the gaps defines channels for transistors. In one aspect, the present invention employs an angled first ion implantation to provide a “halo” of implanted ions extending under at least one spacer at one edge of each of the gaps. In another aspect, the present invention employs a first ion implantation at normal or near normal incidence through the gaps. A gate material, which may include polycrystalline silicon, is formed in the gaps and on the series of layers. Chemical-mechanical polishing removes the gate material from the series of layers, leaving gate material forming a gate in each of the gaps. The series of layers that defined the openings are sequentially removed using one or more directional etching processes, leaving the dielectric spacers that were formed from the blanket dielectric layer on the sidewalls of the openings around the gates. A second ion implantation forms a source and a drain to either side of each gate. Conventional processing then completes FETs forming the integrated circuit through fabrication of self-aligned silicide contacts, pre-metal dielectric layers and metallized inter-level contacts.
As a result, a gate width is realized that is smaller than the first width of the opening by an amount that is equal to twice the thickness of the blanket dielectric layer. The implanted channel is self-aligned to the gate, reducing processing complexity. The source and drain implants are also self-aligned with respect to the gates and result in reduced capacitance, increasing operating frequency for the FETs.


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