Self-aligned floating gate for memory application using...

Details Self-aligned floating gate for memory application using... Self-aligned floating gate for memory application using...

1999-06-28

2001-05-08

Thomas, Tom (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S201000, C438S211000, C438S266000, C438S294000, C438S295000, C438S296000, C438S263000, C438S264000, C257S314000, C257S315000, C257S316000, C257S317000, C257S318000, C257S319000, C257S320000

Reexamination Certificate

active

06228713

ABSTRACT:

BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor memory devices and more particularly to the fabrication of a self aligned floating gate using Shallow trench isolation.
2) Description of the Prior Art
More efficient utilization of device area in VLSI technology is a prominent objective in order to increase the density and number of devices and memory cells on a semiconductor chip. This reduces cost and increase the speed of operation. A known technique is to place various elements, i.e., shallow trench isolation (STI), transistors, capacitors, etch in trenches to achieve greater element density.
A deficiency with current memory devices is the poor quality of the intergate dielectric layers between the floating gate (FG) and the control gate (CG) which causes low breakdown voltages. The inconsistent quality of the intergate dielectric layers worsens as the devices are further shrunk and the intergate dielectric layers are made thinner.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,382,534 (Sheu et al.) shows a method for forming a recessed SID regions. U.S. Pat. No. 5,554,550 (Yang) shows a method for forming a gate in a trench.
However there is still a need for an improved memory cell formation and isolation method.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a memory device with improved intergate dielectric performance and increased floating gate (FG) to control gate (CG) breakdown voltage.
It is an object of the present invention to provide a method for fabricating a memory device which separates any corners of the floating gate (FG) and control gate (CG) layers to improve the intergate dielectric performance and increase floating gate (FG) to control gate (CG) breakdown.
It is an object of the present invention to provide a method for fabricating a memory device that defines the floating gate (FG) using the shallow trench isolation (STI) trench etch thereby reducing the masking and etching steps and creates a self-aligned structure.
To accomplish the above objectives, the present invention provides a method for patterning the poly gate and etching a shallow trench isolation (STI) trench in one mask/etch step.
The invention patterns the floating gate (FG) with the trench etch. The shallow trench isolation (STI) is formed above the top surface of the floating gate (FG). The corners of the floating gate (FG) are adjacent to the sidewalls of the shallow trench isolation (STI). Also, the corner of the control gate (CG) and are separated away from the floating gate (FG) corner. This separation of floating gate (FG) and control gate (CG) corners improves the stability, performance and reliability of the intergate dielectric layer (especially formed of ONO).
In slightly more detail, a preferred embodiment includes: providing a substrate having a cell area and a peripheral area. We form an first dielectric layer (gate oxide) and a first conductive layer (polysilicon layer) over the substrate. Then, a masking layer having first openings is formed over the conductive layer. The first opening defining isolation areas in the substrate where isolation regions will be formed. Using the masking layer as an etch mask, we etch through the first dielectric oxide layer and the conductive layer and into the substrate to form a trench. The remaining first dielectric layer and conductive layer comprise a tunnel dielectric layer and a floating gate of a memory device. The trench defining active regions and the isolation areas in the substrate. We fill the trench with an isolation layer to form isolation regions. We remove the masking layer; We deposit an intergate dielectric layer over the floating gate and the isolation layer. We form a second conductive layer (control gate layer) on the intergate dielectric layer over the floating gate. We pattern the second conductive layer, the intergate dielectric layer, the floating gate and the first dielectric layer to form memory gate structures comprising a control gate; a intergate dielectric; the floating gate; and the tunnel dielectric layer. We form doped regions in the substrate adjacent to the memory gate structures; thereby completing memory devices.
The invention has the following benefits:
no poly wrap around effect
the shallow trench isolation (STI)
24
reduces the sharp corner effect of a LOCOS isolation method thereby improving the intergate dielectric (ONO)
30
layer performance.
reduce the probability of twin bit failure from the bottom gate by using the gap fill as isolation
24
due to no ONO fence formation. Usually Flash or EPROM are placed very close to use maximum silicon area. By a LOCOS method due to the ONO fence formed beside floating gate, the material of floating gate or controlled gate may get trapped and create an electrical short (Known as twin bit failure).
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.


REFERENCES:
patent: 5208179 (1993-05-01), Ozakawa
patent: 5382534 (1995-01-01), Sheu et al.
patent: 5554550 (1996-09-01), Yang
patent: 5731237 (1998-03-01), Sato
patent: 5981341 (1999-11-01), Kim et al.

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