Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-07-05
2009-02-03
Smith, Zandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S153000, C438S154000, C438S218000, C438S219000, C438S275000, C438S938000, C257SE21632, C257SE21639, C257SE21640
Reexamination Certificate
active
07485521
ABSTRACT:
Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a previously deposited stressed layer. A mask position used to pattern the sacrificial layer is adjusted such that removal of the latter deposited stressed layer, using the sacrificial layer, leaves the dual stress layers in an aligned form. The methods result in dual stressed layers that do not overlap or underlap, thus avoiding processing problems created by those issues. A semiconductor device including the aligned dual stressed layers is also disclosed.
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Tessier Brian L.
Zhong Huicai
Zhu Huilong
Advanced Micro Devices, Inc. (AMD)
Hoffman Warnick LLC
International Business Machines - Corporation
Li Todd M C
Nicely Joseph C
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