Self-aligned dual-floating gate memory cell and method for...

Details Self-aligned dual-floating gate memory cell and method for... Self-aligned dual-floating gate memory cell and method for...

2005-02-22

2005-02-22

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000

Reexamination Certificate

active

06858501

ABSTRACT:
An integrated circuit that includes a first dual-floating gate memory cell having a first floating gate isolated from a second floating gate for storing at least one bit of datum, and a second dual-floating gate memory cell having a third floating gate isolated from a fourth floating gate for storing at least one bit of datum, wherein the first dual-floating gate memory cell and the second dual-floating gate memory cell share a control gate, wherein the second floating gate of the first dual-floating gate memory cell shares an oxide layer with the third floating gate of the second dual-floating gate memory cell, and wherein the oxide layer electrically insulates the second and third floating gates from the control gate.

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