Self aligned dual damascene process and structure with low paras

Details Self aligned dual damascene process and structure with low paras Self aligned dual damascene process and structure with low paras

1999-08-06

2000-10-17

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438624, 438618, 438622, 438638, 257758, 257761, 257760, 257776, H01L 214763

Patent

active

061331449

ABSTRACT:
An improved and novel process for fabricating unique interconnect conducting lines and via contact structures has been developed. Using this special self aligned dual damascene process, special interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of double etch stop or etch barrier layers. The key process step of this invention is special patterning of the etch stop or etch barrier layer. This is the advantage of this invention over Prior Art processes that need a continuous, thick stop layer that has a etching selectivity to silicon dioxide, SiO.sub.2 (increasing parasitic capacitance). However, in this invention a self aligned dual damascene process and structure is presented that is easier to process and has low parasitic capacitance. Repeating the self aligned dual damascene processing steps, constructs multilevel conducting structures. This process reduces processing time, reduces the cost of ownership, (compatible with low dielectric constant materials) and at the same time produces a product with superior lines and via contact structures (by use of special etch stop or etch barrier layer patterning), hence improving reliability.

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patent: 5926732 (1999-07-01), Matsuura

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