Self-aligned drain/channel junction in vertical pass...

Details Self-aligned drain/channel junction in vertical pass... Self-aligned drain/channel junction in vertical pass...

2005-08-16

2005-08-16

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S270000, C438S282000, C438S290000, C438S291000, C438S525000, C438S527000

Reexamination Certificate

active

06930004

ABSTRACT:
A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle θ+δ with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle θ with respect to vertical of a dopant into the channel below the source.

REFERENCES:
patent: 5548148 (1996-08-01), Bindal
patent: 6414347 (2002-07-01), Divakaruni
patent: 6440793 (2002-08-01), Divakaruni
patent: 6740920 (2004-05-01), Chidambarrao et al.
patent: 2002/0096219 (2002-07-01), Frasure
“Vertical Pass Transistor Design For Sub-100nm DRAM Technologies” K. McStay, et al., Proceedings 2002 Symposium on VLSI Technology, Section 18.3, pp 180-181 Jun. 11, 2002.

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