Self-aligned contact process using stacked spacers

Details Self-aligned contact process using stacked spacers Self-aligned contact process using stacked spacers

2001-06-07

2002-04-30

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S306000, C438S666000

Reexamination Certificate

active

06380042

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a self-aligned contact process. In particular, the present invention relates to a self-aligned contact process using a nitride sidewall spacer stacked on an oxide sidewall spacer.
2. Description of the Related Art
The self-aligned contact (SAC) process is a powerful method used in semiconductor manufacturing, such as trench type DRAM, stacked DRAM, and FLASH memory, to reduce chip size by shortening the separation between adjacent polysilicon gates. In conventional SAC process, a sidewall spacer of the gate is used to define a lightly doped drain (LDD) structure, and also used to extend the oxide region at the gate edge and improve source/drain leakage property.
FIGS. 1A
to
1
F depict cross-sectional diagrams of prior art SAC process. Referring to
FIG. 1A
, a P-type silicon substrate
10
comprises a gate insulating layer
12
, a plurality of gate structures
14
formed on the gate insulating layer
12
, and a plurality of N
−
-type ion-doped regions
16
formed surrounding the gate structure
14
on the substrate
10
. Each of the gate structures
14
is stacked by a polysilicon layer
18
and a silicon nitride cap layer
20
. Referring to
FIG. 1B
, a nitride (Si
3
N
4
) sidewall spacer
22
is formed on the sidewall of the gate structure
14
, and then an N
+
-type ion-doped region
24
is formed on the exposed N
−
-type ion-doped region
16
using the gate structure
14
and the nitride sidewall spacer
22
as the mask. The N
+
-type ion-doped region
24
serves as a source/drain region, and the remaining part of the N
−
-type ion-doped region
16
serve as a LDD structure. Next, a barrier layer
26
made of silicon nitride is deposited to cover the entire surface of the substrate
10
.
Referring to
FIG. 1C
, an inter-layered dielectric (ILD)
28
is deposited on the barrier layer
26
to fill the gap between adjacent gate structures
14
. Then, a chemical-mechanical polishing (CMP) process is performed to level the surface of the ILD
28
, as shown in FIG.
1
D. Next, as shown in
FIG. 1E
, by using a patterned photo-resist layer (not shown) as a mask, the ILD
28
positioned between adjacent gate structures
14
is removed with the barrier layer
26
as an etching stop layer, resulting in an opening
29
. However, in practical operation, the silicon nitride cap layer
20
and the nitride sidewall spacer
22
are over-etched, thus the profile of the opening
29
is shown as the dotted line. Finally, referring to
FIG. 1F
, the barrier layer
26
at the bottom of the opening
29
is removed to expose the N
+
-type ion-doped region
24
between adjacent gate structures
14
so as to complete a contact hole
30
.
According to the prior art SAC process, the sidewall spacer, for example the nitride sidewall spacer
22
covered on the gate structure
14
, appears as a closed umbrella, not an opened umbrella, such as at least two sidewall spacers stacked on the gate structure. Also, the nitride sidewall spacer
22
covered on the gate structure
14
has the drawback of worsening the leakage problem. It may decrease the electric properties of an IC device, especially for FLASH memory products.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a self-aligned contact process with stacked sidewall spacers to solve the leakage problem.
The self-aligned contact process of the present invention includes the steps: (a) providing a semiconductor substrate having at least two gate structures and a plurality of first ion-doped regions formed at opposite sides of the gate structures on the semiconductor substrate, each of the gate structures having a gate layer and a cap layer formed on the gate layer;
(b) forming a plurality of first sidewall spacers on the sidewalls of the gate structures respectively; (c) forming a plurality of second ion-doped regions on the exposed first ion-doped regions respectively, the depth and concentration of the second ion-doped region being greater than the depth and concentration of the first ion-doped region; (d) forming a first dielectric layer on the entire surface of the semiconductor substrate to fill the gap between adjacent first sidewall spacers; (e) removing the topmost portion of the first sidewall spacers and part of the first dielectric layer to expose each cap layer of the gate structures; (f) forming a plurality of second spacers on the exposed sidewalls of the cap layers respectively; (g) forming a second dielectric layer on the entire surface of the semiconductor substrate to fill the gap between adjacent second sidewall spacers; and (h) performing a dry etching process to remove the second dielectric layer and the first dielectric layer positioned between adjacent gate structures to expose the second ion-doped region so as to form a contact hole.
It is an advantage of the present invention that the first sidewall spacer and the second sidewall spacer stacked thereon, appears as an open umbrella. Also, the sidewall of the gate layer is only covered by the first sidewall spacer, preferably of silicon oxide, thus reducing the leakage phenomenon of the gate structure.
This and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.


REFERENCES:
patent: 6225176 (2001-05-01), Yu
patent: 6281862 (2001-08-01), Sanchez

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