Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2004-06-15
2011-12-20
Blum, David S (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S259000, C438S271000, C438S299000, C438S589000, C257S330000, C257S332000, C257S382000, C257S412000, C257SE21585, C257SE29260, C257SE29262
Reexamination Certificate
active
08080459
ABSTRACT:
A method of fabricating a self-aligned contact in a semiconductor device, in accordance with one embodiment of the present invention, includes etching a trench in a core area and partially extending into a termination area of a substrate. A first oxide is grown on the substrate proximate the trench. A polysilicon layer is deposited in the core area and the termination area. The polysilicon layer is selectively etched to form a gate region in the core area portion of the trench. The etching of the polysilicon layer also forms a first portion of a gate interconnect region in the termination area portion of the trench and a second portion in the termination area outside of the trench.
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“Effects on Selecting Channel Direction in Improving Performance of Sub-100 nm MOSFETs Fabricated on (110) Surface Si Substrate” Japanese Journal of Applied Physics, Part 1, vol. 43, No. 4B, Apr. 2004 pp. 1723-1728 (Nakamura et al.), XP00122768.
Blum David S
Snow Colleen E
Vishay-Siliconix
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