Self-aligned contact for closely spaced transistors

Details Self-aligned contact for closely spaced transistors Self-aligned contact for closely spaced transistors

1999-11-23

2001-09-25

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S241000, C438S586000, C438S635000, C438S637000

Reexamination Certificate

active

06294449

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is integrated circuit processing, in particular, forming self-aligned contacts.
BACKGROUND OF THE INVENTION
In arrays of closely spaced transistors, such as in DRAM memory arrays, it is known to form a self-aligned contact as illustrated in
FIG. 1
, in which two closely spaced transistors have an aperture formed in the area between them, which is also the location of a bitline buried in the substrate.
Sidewall spacers
35
(preferably oxide) isolate the contact from the two gates. It should be noted that there is a thick nitride cover
50
(illustratively 200 nm thick) over the gate stack that protects the gate during the etching process that forms the aperture for the contact. Unfortunately, this thick layer produces variation in linewidth across the chip that is unacceptable for high performance logic applications. The term high performance logic chips as used here means the transistor generation with very short gate length (on the order of 0.1 um Leff). These short gate length features on a logic chip require extremely precise control of physical dimensions and can tolerate only very small ACLV (across chip linewidth variation) to provide high performance, since the gate length has a direct effect on the current output of the transistor. The use of standard DRAM processing such as a thick nitride cap gate stack does not produce acceptable ACLV. In order to fulfill the ACLV requirement, standard logic process typically uses a simpler and thinner gate stack as seen in FIG.
2
. With such a thinner gate stack, the variation on final gate length associated with processing is significantly smaller and able to satisfy the ACLV requirements.
SUMMARY OF THE INVENTION
The invention relates to forming a self-aligned contact that is compatible with high performance logic processing. A feature of the invention is the use of a pair of transistors with standard logic gate stack containing only doped polysilicon
30
(illustratively 100 nm thick) on gate oxide where self-aligned contacts to be formed in the space between the transistor pair. The polysilicon is pre-doped to obtain low resistance for the gate contact. In the conventional DRAM thick gate stack, this low resistance is achieved by building a composite stack with silicide metal over polysilicon.
Once the gates are completed with sidewall spacer
35
, followed by the use of a conventional logic process to deposit the etch stop nitride layer
55
and BPSG dielectric layer
60
over the gates, a photo process defines the contact opening in the dielectric which is self-aligned between the transistor pair as depicted in FIG.
2
. As in standard processing, a cap nitride liner
55
is used as a first etch stop in the initial partial BPSG dielectric etch removal (FIG.
2
). A feature of the present invention is the deliberate removal of that nitride liner in a shoulder region of the gate adjacent to the contact (FIG.
3
); followed by removal of the remaining BSPG dielectric film in the contact area (FIG.
4
). With nitride liner protecting the contact area at the bottom of the aperture, the exposed polysilicon gate shoulder is then oxidized (FIG.
5
). The remaining nitride liner is then removed to open up the contact (FIG.
6
).


REFERENCES:
patent: 5470777 (1995-11-01), Nagata et al.
patent: 5989959 (1999-11-01), Araki
patent: 6082828 (2000-07-01), Lin et al.
patent: 6146994 (2000-11-01), Hwang
patent: 6162675 (2000-12-01), Hwang et al.

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