Self-aligned conductive line for cross-point magnetic memory...

Details Self-aligned conductive line for cross-point magnetic memory... Self-aligned conductive line for cross-point magnetic memory...

2001-08-03

2004-02-17

Huff, Mark F. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S313000, C430S314000, C430S316000, C430S317000, C430S318000, C430S319000, C427S127000, C438S003000

Reexamination Certificate

active

06692898

ABSTRACT:

FIELD OF THE INVENTION
The preferred embodiment of the present invention generally relates to cross-point magnetic memory integrated circuits (ICs). More particularly, the preferred embodiment relates to self-aligned conductive lines for cross-point magnetic memory ICs.
BACKGROUND OF THE INVENTION
“
FIG. 1
a
shows a cross-section of magnetic memory IC
101
. The memory IC comprises a plurality of magnetic memory cells in an array region
103
of the IC. The cells each comprises a magnetic stack
120
sandwiched between upper and lower metal lines
140
and
150
. The upper and lower metal lines run in orthogonal directions embedded in interlevel dielectric (ILD) layers
110
a
and
110
b
. The upper and lower metal lines serve as bitlines and wordlines of the memory array. A cell is located at an intersection of a bitline and wordline.”
The alignment of the various layers of the memory cells become more critical as ground rules decreases. For example, misalignments among the layers can result in line-to-line and/or level-to-level electrical shorts.
SUMMARY OF THE INVENTION
As evident from the foregoing discussion, it is desirable to provide a process for forming magnetic memory cells which avoids or reduces misalignments of the various layers used to form the cells.
In a first aspect, the present invention provides a method of forming a magnetic memory device. A first plurality of conductive lines (e.g., bitlines or wordlines)are formed over a semiconductor workpiece. A plurality of magnetic material lines are formed over corresponding ones of the first plurality of conductive lines. A second plurality of conductive lines are formed over the semiconductor workpiece. The second plurality of conductive lines cross over the first conductive lines and the magnetic material lines. These second lines, which can serve as either the bitline or wordline, can be used as a mask to while portions of the magnetic material lines are removed.
In another aspect, the present invention provides another method of forming an integrated circuit device. This method can be combined with the first method described but does not need to be. In this method, a magnetic material layer is formed over a workpiece and a metallic hard mask is formed over the magnetic material layer. The metallic hard mask is patterned and used as a mask to etch portions of the magnetic material layer. A dielectric layer is formed over remaining portions of the magnetic material layer. A chemical-mechanical polish can then be performed to planarize the dielectric layer. The metallic hard mask can serve as an etch stop for the chemical-mechanical polish.
In yet another aspect, the present invention provides another technique that can be combined with either or both of the above-mentioned methods. This method can also be used independently. In this method, an insulating layer is formed over a magnetic material layer. A number of trenches are formed in the insulating layer and filled by a conductive material to form a plurality of conductive lines. Remaining portions of the insulating layer are then removed. Portions of the magnetic material layer can then be removed using the conductive lines as a mask.
In its various aspects, the present invention has a number of advantages over prior art methods. Some of these advantages of certain embodiments include avoiding the short between first conductive lines
140
and second conductive lines
150
. The problem that is avoided can be clearly seen in
FIG. 1
b
where the misalignment of the second conductive line
150
to magnetic stack
120
results in an electrical short between the first and second conductive lines
140
and
150
.
Aspects of the present also have the advantage that additional process steps that are required to prevent M
2
to M
3
shorting, such as a dielectric deposition and planarization to form the isolation in between the magnetic stacks
120
can be avoided. As a result, reductions in cost are achieved. Yield can also be increased.


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