Self aligned bit-line contact opening and node contact...

Details Self aligned bit-line contact opening and node contact... Self aligned bit-line contact opening and node contact...

2000-10-16

2002-08-27

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S655000, C438S664000

Reexamination Certificate

active

06440791

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89120747, filed Oct. 5, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory fabrication process. More particularly, the present invention relates to a self-aligned bit-line contact and node contact fabrication process.
2. Description of the Related Art
In the existing semiconductor fabrication processes, self-aligned contact (SAC) fabrication processes are often used to increase the alignment margin of the contact opening. The steps in the self-aligned contact process are as follows: a metal oxide semiconductor (MOS) gate and a cap layer above the gate are formed. A spacer is formed on a sidewall of the gate and cap layer. A dielectric layer is deposited over the substrate. A lithography and an etching process are conducted, to etch a self-aligned contact opening in the dielectric layer, on opposite sides of the gate. The self-aligned contact opening has a width greater than the distance between the gates, to assure that the source/drain region of the MOS is exposed. During the etching process, the gate are protected by the cap layer and the spacer. Thus, the gate is not exposed. The self-aligned contact is very wide. Consequently, even if there is a significant error in alignment, the contact opening formed in later steps is able to make contact with the source/drain region, which indicates that the alignment margin of the self-aligned contact is very high.
In the fabrication process of a memory, the self-aligned contact openings that must be formed above the source/drain region in the MOS of the memory cell are the self-aligned bit-line contact and self-aligned node contact, respectively. In the memory, gate contacts are located on some periphery MOS gates to form an electrically connection with the periphery gate contacts, so that to control the turn-on and turn-off of the periphery MOS can be controlled. The fabrication process of a self-aligned contact and periphery gate contact in a conventional memory is outlined below.
As shown in
FIG. 1A
, a substrate
100
having memory cell MOS
120
and periphery MOS active region
110
is provided, wherein gate dielectric layer
122
has been formed over periphery MOS active region
110
, periphery MOS gate
130
a
has been formed over gate dielectric layer
122
, cap layer
133
a
, composed of silicon nitride, has been formed over periphery MOS gate
130
a
and lightly doped drains (LDD)
150
have been formed in the substrate on opposite sides of MOS gate
130
a
. Memory cell MOS
120
includes gate dielectric layer
122
, memory cell MOS gate
130
b
above gate dielectric layer
122
, cap layer
133
b
, composed of silicon nitride, above memory cell MOS gate
130
b
, and memory cell source/drain region
154
in substrate
100
on opposite sides of memory cell MOS gate
130
b
. Isolation layer
120
isolates memory cell MOS
120
. Conformal liner oxide layer
142
and a silicon nitride layer (not shown) are formed sequentially over substrate
100
. Liner oxide layer functions to reduce the stress of the silicon nitride layer. An anisotropic etching operation is performed on the silicon nitride layer, to form spacer
143
a
on the sidewall of the periphery MOS gate
130
a
and cap layer
133
a
. At the same time spacer
143
b
is formed on the sidewall of memory cell MOS gate
130
b
and cap layer
133
b
. It should be pointed out that the specification uses the processing steps of periphery MOS active region
110
to represent the processing steps used for the NMOS active region and PMOS active region, in the periphery circuit. In this manner, the description can further simplified.
As shown in
FIG. 1B
, two photolithographic processes are performed respectively on the NMOS active region and PMOS active region, in order to form photoresist layer
158
, which covers memory cell MOS
120
. As mentioned above, the specification uses the processing steps of periphery MOS active region
110
to represent processing steps used for the NMOS active region and PMOS active region, in the periphery circuit. Thus, photoresist layer
158
represents the two layers formed as a result of two photolithographic processes on the top portion of the memory cell MOS
120
. Using photoresist layer
158
, cap layer
133
a
and spacer
143
a
as a mask, ions
159
are implanted to form a periphery source/drain region in substrate
100
, on opposite sides of spacer
143
a
. This step completes the fabrication of periphery MOS
110
a.
The specification uses the processing steps of periphery MOS active region
110
to represent processing steps used for the NMOS active region and PMOS active region, in the periphery circuit. Thus, the etching of spacer
143
a
and the step of implanting ions
159
, represent each spacer etching step and ion implantation step for both the periphery NMOS active region and PMOS active region.
As shown in
FIG. 1C
, substrate
100
is covered by silicon oxide layer
170
. A third photolithography and an etching process are performed to form self-aligned bit-line contact opening
175
, self-aligned node contact opening
176
, and periphery gate contact opening
177
in silicon oxide layer
170
. At the same time, liner oxide layer
142
, exposed by self-aligned bit-line contact opening
175
and self-aligned node contact opening
176
, is removed. Self-aligned bit-line contact opening
175
and self-aligned node contact opening
176
expose memory cell source/drain region
154
. The width of contact openings
175
and
176
is greater than the distance between memory cell MOS gate
130
b
. Periphery gate contact opening
177
exposes cap layer
133
a
of periphery MOS
110
a.
As shown in
FIG. 1D
, a fourth photolithographic process is performed to cover the memory cell MOS
120
with photoresist layer
180
used to protect cap layer
133
b
and spacer
143
b
of the memory cell MOS. A silicon nitride etching step is performed to etch through cap layer
133
a
of the memory MOS cell, exposing periphery MOS gate
130
a
, in order to connect MOS gate
130
a
and the contact opening, formed in a subsequent step.
The above description and accompanying illustrations, reveal a characteristic in the fabrication process of a conventional memory self-aligned contact opening and periphery gate contact opening. Between the completion of memory cell source/drain region
154
and the lightly doped drain (LDD)
150
of periphery MOS
110
a
and the completion of contact openings
175
,
176
, and
177
, a total of four photolithographic processes are performed. First, during the formation of periphery source drain region
160
, two photolithographic processes are required. During the formation of periphery gate contact opening
177
and self-aligned bit-line (node) contact openings
175
(
176
), a third photolithographic process is required. During the etch-through of cap layer
133
a
of the periphery MOS a fourth photolithographic process is required. The excessive number of photolithographic etching steps, makes the conventional fabrication process more complicated. Additionally, because a great portion of the cap layer composed of silicon nitride may be consumed during the etching of the self-aligned bit-line (node) contact opening
175
(
176
), cap layer
133
b
must be rather thick, which often causes excessive stress.
SUMMARY OF THE INVENTION
The present invention provides a self-aligned bit-line contact opening and node contact opening fabrication process, that only requires three photolithographic etching steps to form the periphery MOS source/drain region, the periphery gate contact opening and the self-aligned bit-line (node) contact opening, and etching of the cap layer above the periphery MOS gate. The steps of the fabrication process are as follows: a substrate is provided having a periphery MOS active region and memory cell MOS, wherein the periphery MOS active region has a first gate, and a cap layer above the first gate, and further wherein the memory ce

Affiliated with

Also associated with

Rating

Self aligned bit-line contact opening and node contact... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self aligned bit-line contact opening and node contact..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self aligned bit-line contact opening and node contact... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2881009