Selectively updateable mapped data storage system

Details Selectively updateable mapped data storage system Selectively updateable mapped data storage system

1998-07-28

2000-10-03

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

365 49, 365 50, G06F 1200

Patent

active

061286974

ABSTRACT:
A selectively updateable mapped data storage system is provided. The data storage system includes an address decoder two improved CAM blocks, and a converter connected between the two improved CAM blocks. This selectively updateable mapped data storage system can be implemented with a smaller layout space on the chip and consumes less electrical power than the prior art. Moreover, this selectively updateable mapped data storage system allows the selective updating procedure to be easily and more efficiently implemented than through software means. The selectively updateable mapped data storage system is therefore more advantageous and cost-effective to use than the prior art.

REFERENCES:
patent: 5428759 (1995-06-01), Smith et al.
patent: 5475825 (1995-12-01), Yonezawa et al.
patent: 5574875 (1996-11-01), Stansfield et al.
patent: 5682495 (1997-10-01), Beavers et al.
patent: 5953748 (1996-11-01), Riordan
patent: 6014732 (2000-01-01), Naffziger

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