Selectively changeable line width memory

Details Selectively changeable line width memory Selectively changeable line width memory

2008-07-29

2008-07-29

Nguyen, Hiep T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

Reexamination Certificate

active

11160184

ABSTRACT:
The invention provides for selectively changing a line width for a memory, i.e., selecting one of a plurality of line widths for a memory. The selected line width is used in communicating with one or more processors. This provides increased flexibility and efficiency for communicating with the memory. In particular, a register can be set based on a desired line width, and subsequently used when locating data in the memory. The selected line width can be associated with each data block in the memory to allow multiple line widths to be used simultaneously. When implemented in a cache, multiple ways of the cache can be processed as a group to provide data during a single memory operation. The line width can be varied based on a task, a processor, and/or a performance evaluation.

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“Dynamically Variable Line-Size Cache Expoliting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs”, IEEE, Jan. 9, 1999, pp. 218-222.

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