Selective wet etch process for CMOS ICs having embedded...

Details Selective wet etch process for CMOS ICs having embedded... Selective wet etch process for CMOS ICs having embedded...

2011-05-17

2011-05-17

Lee, Hsien-ming (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C257S274000, C257S338000, C257SE21632, C257SE21634, C257SE21619

Reexamination Certificate

active

07943456

ABSTRACT:
A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes providing a substrate having a semiconductor surface including PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate stack including a gate electrode layer is formed on a gate dielectric layer in or on both the PMOS regions and the NMOS regions. An n-type doping is used to create n-type wet etch sensitized regions on opposing sides of the gate stack in both the PMOS and said NMOS regions. Wet etching removes the n-type wet etch sensitized regions in (i) at least a portion of said PMOS regions to form a plurality of PMOS source/drain recesses or (ii) in at least a portion of said NMOS regions to form a plurality of NMOS source/drain recesses, or (i) and (ii). At least one of a compressive strain inducing epitaxial layer is formed in the plurality of PMOS source/drain recesses and a tensile strain inducing epitaxial layer is formed in the plurality of NMOS source/drain recesses. The fabrication of the IC is then completed.

REFERENCES:
patent: 7060576 (2006-06-01), Lindert et al.
patent: 7244654 (2007-07-01), Chidambaram et al.
patent: 7315063 (2008-01-01), Lee et al.
patent: 2008/0242017 (2008-10-01), Lee et al.
patent: 2009/0291540 (2009-11-01), Zhang et al.

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