Selective W CVD plug process with a RTA self-aligned W-silicide

Details Selective W CVD plug process with a RTA self-aligned W-silicide Selective W CVD plug process with a RTA self-aligned W-silicide

1997-10-20

2000-04-11

Nelms, David

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438682, 438683, 438785, 438787, H01L 2144

Patent

active

060487941

ABSTRACT:
The present invention provides a method of fabricating a tungsten (W) plug 36 contact to a substrate using a selective W CVD Process with a self-aligned W-Silicide Barrier layer 34. The method comprises the steps of: forming first insulating layer 20 over a silicon semiconductor substrate 10; forming a first (contact) opening 24 in the first insulating layer 20 exposing the surface of the substrate; selectively growing a thin first tungsten layer 30 over the exposed substrate surface; rapidly thermally annealing the substrate forming a thin first tungsten silicide layer 34 from the thin first tungsten layer 30; selectively depositing a tungsten plug 36 over the first thin tungsten silicide layer 34 substantially filling the first opening 36 thereby forming a W plug contact. The RTA/W silicide layer 34 lowers the contact resistance, increases the adhesion and facilitates the selective deposition of the W plug 36.

REFERENCES:
patent: 5554565 (1996-09-01), Liaw et al.
patent: 5599739 (1997-02-01), Merchant et al.
patent: 5604158 (1997-02-01), Cadien et al.
patent: 5627400 (1997-05-01), Koga

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