Selective uniaxial stress modification for use with strained...

Details Selective uniaxial stress modification for use with strained... Selective uniaxial stress modification for use with strained...

2006-07-06

2011-10-18

Lindsay, Jr., Walter L (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S300000, C438S301000, C257SE21430, C257SE21431

Reexamination Certificate

active

08039341

ABSTRACT:
A semiconductor fabrication process includes masking a first region, e.g., an NMOS region, of a semiconductor wafer, e.g., a biaxial, tensile strained silicon on insulator (SOI) wafer and creating recesses in source/drain regions of a second wafer region, e.g., a PMOS region. The wafer is then annealed in an ambient that promotes migration of silicon. The source/drain recesses are filled with source/drain structures, e.g., by epitaxial growth. The anneal ambient may include a hydrogen bearing species, e.g., H2or GeH2, maintained at a temperature in the range of approximately 800 to 1000° C. The second region may be silicon and the source/drain structures may be silicon germanium. Creating the recesses may include creating shallow recesses with a first etch process, performing an amorphizing implant to create an amorphous layer, performing an inert ambient anneal to recrystallize the amorphous layer, and deepening the shallow recesses with a second etch process.

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M. Yoshimi et al., “Strained-SOI(sSOI) Technology for High Performace CMOSFET in 45-nm-or-below Technology Node”, SSTIC, 2006.

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