Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
1999-10-25
2001-01-30
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S528000
Reexamination Certificate
active
06180487
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to improved Silicon-on-Insulator devices. More particularly, the present invention relates to methods for removing heat from Silicon-on-Insulator devices and devices having such characteristics.
BACKGROUND ART
Silicon-on-Insulator (SOI) technology is of growing importance in the field of integrated circuits. SOI technology involves forming transistors in a relatively thin layer of semiconductor material overlying a layer of insulating material. More particularly, SOI technology is characterized by the formation of a thin silicon layer (device region) for formation of the active devices over an insulating layer, such as an oxide, which is in turn formed over a substrate. Transistor sources and drains are fonned, for example, by implantations into the silicon layer while transistor gates are formed by forming a patterned oxide and conductor layer structure.
Such structures provide a significant gain in performance by having lower parasitic capacitance (due to the insulator layer) and increased drain current due to floating body charging effects (since no connection is made to the channel region and charging of the floating body provides access towards a majority of carriers which dynamically lower the threshold voltage, resulting in increased drain current). Devices, such as metal oxide silicon field effect transistors (MOSFET), have a number of advantages when formed on SOI wafers versus bulk silicon MOS transistors. These advantages include: reduced source/drain capacitance and hence improved speed performance at higher-operating frequencies; reduced N
+
to P
+
spacing and hence higher packing density due to ease of isolation; absence of latchup; lower voltage applications; and higher “soft error” upset immunity (i.e., the immunity to the effects of alpha particle strikes).
Although there are significant advantages associated with SOI technology, there are significant disadvantages as well. For example, poor heat removal from devices on an SOI substrate is a significant disadvantage. Electrical devices generate heat, and the inability to remove or dissipate the heat results in poor and/or inconsistent performance of the electrical devices, or even in some instances device and/or substrate degradation.
There is poor heat removal for devices on SOI substrates primarily because of the oxide insulation layer. This is because the oxide insulation layer has a markedly lower thermal conductivity than the thermal conductivity of conventional bulk silicon (typically used as semiconductor substrates), which typically surrounds semiconductor devices. As a result, the buried oxide layer undesirably thermally insulates the device region in SOI substrates.
In view of the aforementioned disadvantages, there is a need for SOI devices of improved quality, particularly SOI devices having improved heat removal characteristics, and more efficient methods of making such SOI devices.
SUMMARY OF THE INVENTION
As a result of the present invention, an SOI substrate having improved heat removal characteristics is provided. By forming an SOI substrate according to the present invention, improved performance of devices subsequently formed on the SOI substrate is facilitated. Moreover, forming an SOI substrate in accordance with the present invention does not degrade or deleteriously effect the advantageous properties and characteristics commonly associated with SOI technology (improved speed performance at higher-operating frequencies, higher packing density, absence of latch-up, lower voltage applications, and higher “soft error” upset immunity).
In one embodiment, the present invention relates to a method of forming a Silicon-on-Insulator substrate involving the steps of providing a monocrystalline silicon substrate; patterning a mask over the monocrystalline silicon substrate thereby exposing a portion of the monocrystalline silicon substrate; implanting a first dosage of oxygen atoms in the exposed portion of the monocrystalline silicon substrate; removing the mask from the monocrystallinc silicon substrate; implanting a second dosage of oxygen atoms without using an implantation mask in the monocrystalline silicon substrate; and annealing the oxygen implanted monocrystalline silicon substrate to provide the Silicon-on-Insulator substrate.
In another embodiment, the present invention relates to a method of dissipating heat from a silicon device layer of a Silicon-on-Insulator substrate comprising a monocrystalline silicon layer, a buried oxide layer over the monocrystalline silicon layer, and the silicon device layer over the buried oxide layer involving the steps of forming the buried oxide layer by patterning a mask over the monocrystalline silicon layer thereby exposing a portion of the monocrystalline silicon layer; implanting a first dosage of oxygen atoms in the exposed portion of the monocrystalline silicon layer to form a discontinuous oxygen layer; removing the mask from the monocrystalline silicon layer; implanting a second dosage oxygen atoms in the monocrystalline silicon layer to form a substantially continuous oxygen layer; and annealing the substantially continuous oxygen layer to provide the Silicon-on-Insulator substrate, the buried oxide layer of the Silicon-on-Insulator substrate having a thin portion and a thick portion, wherein heat is dissipated through the thin portion of the buried oxide layer.
In yet another embodiment, the present invention relates to a Silicon-on-Insulator structure containing a monocrystalline silicon layer; a buried oxide layer over the monocrystalline silicon layer, the buried oxide layer including a first region having a first thickness and a second region having a second thickness, wherein the first thickness is from about 30% to about 70% smaller than the second thickness; a silicon device layer over the buried oxide layer; and a heat generating device on the silicon device layer and positioned over the first region of the buried oxide layer.
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Advanced Micro Devices , Inc.
Amin, Eschweiler & Turocy
Fourson George
Garcia Joannie A.
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