Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-07
2002-05-28
Fahmy, Jr., Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S200000, C438S222000, C438S357000, C438S526000, C257S357000, C257S372000
Reexamination Certificate
active
06395591
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method in a semiconductor fabrication process, and more particularly to a method in a CMOS fabrication process for decoupling noisy and quiet electrical grounds.
2. Description of the Related Art
Semiconductor fabrication processes for manufacturing integrated circuits use a starting material of either a p-type substrate or an n-type substrate. The p-type substrate is more prevalent in CMOS devices today because, among other things, the body of the integrated circuit thus built can be connected to an electrical ground and is thus compatible with most types of integrated circuit packages. While a lightly doped p-type substrate having a resistivity of 5 or 20 ohm-cm has been used in early fabrication processes, this was found to be problematic for CMOS integrated circuits because the high substrate resistance renders the integrated circuit more susceptible to latchup.
One method to improve latchup immunity is to use a heavily doped substrate, i.e. a p++ substrate, with a lightly doped epitaxy layer grown on top. Such a substrate structure is illustrated in FIG.
1
A. The p++ substrate can have a resistivity as low as 0.05 ohm-cm. While the use of a heavily doped p++ substrate can effectively reduce latchup susceptibility, the heavily doped substrate is typically more expensive and can introduce problems such as auto-doping in the manufacturing process. Furthermore, the heavily doped p++ substrate is not desirable for building integrated circuits including analog and digital components. This is because the low resistance of the p++ substrate has the effect of shorting the electrical ground of the digital and power switching circuitry which are typically noisy to the electrical ground of the analog circuitry which needs to be quiet or free from ground noise. A substrate structure including a blanket p++ buried layer in a lightly doped p-type substrate has been proposed and is illustrated in FIG.
1
B. While the use of a p− substrate can avoid problems such as auto-doping, the substrate structure of
FIG. 1B
does not solve the ground noise coupling issue as the ground of the noisy circuitry is still coupled to the ground of the quiet circuitry through the p++ buried layer.
Therefore, it is desirable to provide a CMOS fabrication process which is capable of providing decoupling of the electrical ground for quiet and noisy circuitry while providing immunity against latchup and electrostatic discharge.
SUMMARY OF THE INVENTION
According to the present invention, an integrated circuit fabrication process uses a selective substrate implant process which is capable of providing effective decoupling of a first power supply connection from a second power supply connection while providing immunity against parasitic effects. The first power supply may be a noisy electrical ground connection and the second power supply may be a quiet electrical ground connection.
According to one embodiment of the present invention, a method for forming a CMOS structure includes providing a substrate of a first type, masking a surface of the substrate to selectively expose regions of the substrate, doping the substrate using dopants of the first type to form heavily doped regions, forming an epitaxy layer of the first type on the substrate where the epitaxy layer is more lightly doped than the heavily doped regions, masking a surface of the epitaxy layer to selectively expose a first group and a second group of well regions of the first type where the first group of the well regions are disposed over the heavily doped regions, and doping the epitaxy layer using dopants of the first type to form the well regions of the first type.
The selective substrate implant process of the present invention has particular applications in forming CMOS analog integrated circuits where it is important to decouple the analog ground for noise-sensitive analog circuitry from the often noisy digital ground of the digital and power switching circuitry. The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.
REFERENCES:
Parpia et al., “A CMOS-Compatible High-Voltage IC Process”, IEEE Transaction on Electron Devices, vol. 35,No. 10, Oct. 1988.*
Frei, M. et al, “Integration of High-Q Inductors in a Latch-up Resistant CMOS Technology”, EDM 99, 31.5.1, pp. 757-760, 1999 IEEE.
Alter Martin
Laber Carlos Alberto
McCormack Stephen
Wrathall Robert S.
Fahmy Jr. Wael
Lee Hsien-Ming
Micrel Incorporated
Skjerven Morrill LLP
LandOfFree
Selective substrate implant process for decoupling analog... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Selective substrate implant process for decoupling analog..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective substrate implant process for decoupling analog... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2876409