Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-04-28
2004-11-30
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S770000
Reexamination Certificate
active
06825114
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to the formation of fuses using masks comprising amorphous carbon.
BACKGROUND OF THE INVENTION
In various integrated circuit (IC) applications, it is desirable to produce simple, inexpensive, one-time programmable elements. For example, to assist in the identification of individual integrated circuits (ICs), a number of fuses may be provided in the IC. These fuses can be used to assign a unique identifier or serial number for the IC by “blowing” a selected number of the fuses. This is typically accomplished by running a large amount of current to the fuses that are to be blown to cause melting of the fuse material. The melting and subsequent agglomeration of fuse material dramatically increase the resistance in the fuse. The blown fuses may later be identified by comparing resistance measurements for the blown fuses with that of a reference fuse.
A typical fuse
5
is illustrated in FIG.
1
. Fuse
5
includes a conductive linear region
17
that extends between two terminals
6
. A number of contacts
13
are connected to the terminals for providing current through linear region
17
. Linear region
17
is conventionally formed as a polysilicon layer with a metal silicide layer formed thereon. Because the metal silicide material typically has a lower resistance than the polysilicon material, current will pass through the metal silicide layer.
When an excessive current density (e.g., 10
5
to 10
6
amperes/cm
2
or greater) is provided to linear region
17
, a portion of the metal silicide layer will melt. The melted material will then agglomerate to form a hole in the silicide layer. Current passed through linear region
17
will then be forced to travel through the polysilicon layer. Because the resistivity of the polysilicon layer is greater than that for silicide, the overall resistance of linear region
17
is dramatically increased.
One issue that has been identified with conventional fuses concerns the reliability of the fuses to perform in an expected manner. In certain circumstances, a fuse may not blow even when a high current is applied to the fuse that would normally cause melting and agglomeration of silicide material. Where fuses fail to perform as expected, the fuse may be misprogrammed and may lead to misidentification of the IC in the example of a unique serial number described above.
One reason that fuses may not perform as expected in all situations is that conventional fuses have a limited number of “weak” or “hot” spots where silicide material tends to melt. For example, where a portion of the fuse has a reduced cross-sectional area, a greater amount of current per unit area will be present in the portion, as compared to surrounding areas, causing the “weak” spot having a reduced cross-sectioned area to melt before the surrounding areas. Additional areas of weakness may be found where a relatively sharp corner or transition occurs, such as that found at corners
7
shown in FIG.
1
. If linear portion
17
has a generally uniform cross-section, the areas of weakness for fuse
5
would typically be at corners
7
. While generally a fuse having two weak spots will perform as expected, in certain circumstances these weak spots may not melt even where high current is passed through the weak spots.
Thus, there is a need to form fuses in an integrated circuit that have increased reliability. Further, there is a need to form fuses that have a larger number of weak spots that melt when a large amount of current is provided to the fuse. Even further, there is a need to use an amorphous carbon mask to form fuses. Even further still, there is a need for a method of producing integrated circuit fuses that have increased reliability using a mask comprising amorphous carbon.
SUMMARY OF THE INVENTION
One exemplary embodiment relates to a method of forming a fuse for use in an integrated circuit. The method includes providing a mask material layer over a conductive layer, where the mask material layer comprises amorphous carbon. The method also includes doping the mask material layer with nitrogen, forming an anti-reflective coating (ARC) feature over the mask layer, and removing a portion of the mask layer according to the ARC feature to form a mask. The method further includes removing the ARC feature to form a warped mask, patterning the conductive layer according to the warped mask, and removing the warped mask. The method further includes providing a silicide layer over the patterned conductive layer.
Another exemplary embodiment relates to a method of forming a fuse in an integrated circuit. The method includes depositing a layer comprising amorphous carbon above a layer of polysilicon, introducing nitrogen into the layer comprising amorphous carbon, and forming an anti-reflective coating (ARC) mask over above the layer comprising amorphous carbon. The method also includes patterning the layer comprising amorphous carbon according to the ARC mask to form a mask feature and altering the shape of the mask feature by removing the ARC mask to form a mask feature having a non-linear shape. The method further includes removing a portion of the layer of polysilicon according to the mask feature to form a non-linear polysilicon feature and providing a layer comprising a metal silicide above the non-linear polysilicon feature.
A further exemplary embodiment relates to a fuse for an integrated circuit produced by a method that includes providing a mask material comprising amorphous carbon and nitrogen above a layer of polysilicon. The method also includes providing a cap layer over the mask material, where the cap layer comprises an anti-reflective coating (ARC) material. The method further includes etching the cap layer to form a cap feature, patterning the mask material according to the cap feature to form a mask, and removing the cap feature to warp the mask. The method further includes patterning the layer of polysilicon according to the mask after the cap feature is removed to form a polysilicon feature, removing the mask, and forming a silicide layer above the polysilicon feature.
Other principal features and advantages will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.
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U.S. patent application No. 10/215,173, entitled “Use of Amorphous Carbon Hard Mask for Gate Patterning to Eliminate Requirement of Poly Re-Oxidation”, as filed on Aug. 8, 2002, including claims, drawings, and abstract (29 pages).
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U.S. patent application No. 10/230,794, entitl
Dakshina-Murthy Srikanteswara
Fisher Philip A.
Lyons Christopher F.
Foley & Lardner LLP
Nhu David
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