Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-10-10
2006-10-10
Blum, David S. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S269000
Reexamination Certificate
active
07118960
ABSTRACT:
A memory cell having a bit line contact and a method of manufacturing the memory cell is provided The memory cell may be a 6F2or smaller memory cell. The bit line contact may have a contact hole bounded by insulating side walls, the contact hole may have a selective, epitaxially grown base layer, may be partially or completely filled with a doped polysilicon plug, and may have a silicide cap. The doped polysilicon plug may have an upper plug surface profile that is substantially free of concavities or substantially convex. Similarly, a storage node contact may comprise a doped polysilicon plug having an upper plug surface profile that is substantially free of concavities or that is substantially convex. Additionally, a semiconductor device having a conductive contact comprising a polysilicon plug may is provided. The plug may contact a capacitor structure.
REFERENCES:
patent: 4541169 (1985-09-01), Bartush
patent: 5145802 (1992-09-01), Tyson et al.
patent: 5302844 (1994-04-01), Mizuno et al.
patent: 5326722 (1994-07-01), Huang
patent: 5587338 (1996-12-01), Tseng
patent: 5747844 (1998-05-01), Aoki et al.
patent: 5780343 (1998-07-01), Bashir
patent: 5827770 (1998-10-01), Rhodes et al.
patent: 5901092 (1999-05-01), Tran
patent: 5917213 (1999-06-01), Iyer et al.
patent: 5955757 (1999-09-01), Jen et al.
patent: 5994182 (1999-11-01), Gonzalez et al.
patent: 5994735 (1999-11-01), Maeda et al.
patent: 6025221 (2000-02-01), Brown
patent: 6043562 (2000-03-01), Keeth
patent: 6127209 (2000-10-01), Maeda et al.
patent: 6255160 (2001-07-01), Huang
patent: 6291846 (2001-09-01), Ema et al.
patent: 6300215 (2001-10-01), Shin
patent: 6380576 (2002-04-01), Tran
patent: 6380578 (2002-04-01), Kunikiyo
patent: 6420751 (2002-07-01), Maeda et al.
patent: 6429529 (2002-08-01), Keeth
patent: 6653230 (2003-11-01), Nakamura
patent: 6882006 (2005-04-01), Maeda et al.
patent: 2001008604 (2001-02-01), None
Koga et al., A 0.23 um Double Self-Aligned Contact Cell for Gigabit DRAMs With a Ge-Added Vertical Epitaxial Si Pad, 1996 IEEE, IEDM 96-589-IEDM 96-92.
Hada et al., A Self-Aligned Contact Technology Using Anisotropical Selective Epitaxial Silicon For Giga-Bit DRAMS, IEEE, 1995 IEDM 95-668.
Blum David S.
Dinsmore & Shohl LLP
LandOfFree
Selective polysilicon stud growth does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Selective polysilicon stud growth, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective polysilicon stud growth will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3692525