Selective plating method for forming integral via and wiring lay

Details Selective plating method for forming integral via and wiring lay Selective plating method for forming integral via and wiring lay

1991-08-22

1993-05-11

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156644, 156655, 156656, 1566591, 156668, 205125, B44C 122, B29C 3700, C23F 100

Patent

active

052098176

ABSTRACT:
In a multi-level wiring structure wires and vias are formed by an isotropic deposition of a conductive material, such as copper, on a dielectric base, such as a polyimide. In a preferred embodiment of the invention copper is electroplated to a thin seed conducting layer deposited on the surface of the dielectric base in which via openings have been formed. Openings in a resist formed on the surface of the dielectric base over the seed layer forms a pattern defining the wiring and via conductor features. Electroplated copper fills the via openings and wire pattern openings in the resist isotropically so that the upper surfaces of the wiring and vias are co-planar when the plating step is complete. In adding subsequent wiring levels, the resist is removed and the via conductor and wiring pattern covered with another dielectric layer which both encapsulates the conductors of the previous layer and serves as the base for the next level which is formed in the same manner as the previous level.

REFERENCES:
patent: 4572764 (1986-02-01), Fan
patent: 4631111 (1986-12-01), Williston
patent: 4954214 (1990-09-01), Ho
IBM Technical Disclosure Bulletin, vol. 26, No. 3A; Aug. 1983; "Photosensitive Glass for Producing Recessed Metallurgy, Eliminating Need for Planarization"; R. R. Shaw & R. R. Tummala; p. 1094.

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