Selective oxide trimming to improve metal T-gate transistor

Details Selective oxide trimming to improve metal T-gate transistor Selective oxide trimming to improve metal T-gate transistor

2006-08-01

2006-08-01

Pham, Thanhha (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S231000, C438S275000, C438S591000

Reexamination Certificate

active

07084025

ABSTRACT:
A process to form a FET using a replacement gate. An example feature is that the PMOS sacrificial gate is made narrower than the NMOS sacrificial gate. The PMOS gate is implanted preferably with Ge to increase the amount of poly sacrificial gate that is oxidized to form PMOS spacers. The spacers are used as masks for the LDD Implant. The space between the PLDD regions is preferably larger that the space between the NLDD regions because of the wider PMOS spacers. The PLDD tends to diffuse readily more than NLDD due to the dopant being small and light (i.e. Boron). The wider spacer between the PMOS regions improves device performance by improving the short channel effects for PMOS. In addition, the oxidization of the sacrificial gates allows trimming of sacrificial gates thus extending the limitation of lithography. Another feature of an embodiment is that a portion of the initial pad oxide is removed, thus reducing the amount of undercut created during the channel oxide strip for the dummy gate process. This would improve on the gate overlap capacitance for a T-gate transistor. In a second embodiment, two metal gates with different work functions are formed.

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