Selective implementation of barrier layers to achieve...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S369000, C257S411000

Reexamination Certificate

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07105889

ABSTRACT:
A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2peroxide solution.

REFERENCES:
patent: 5668028 (1997-09-01), Bryant
patent: 5763922 (1998-06-01), Chau
patent: 6040769 (2000-03-01), Payne
patent: 6407435 (2002-06-01), Ma et al.
patent: 6538278 (2003-03-01), Chau
patent: 6831339 (2004-12-01), Bojarczuk et al.

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