Selective high k dielectrics removal

Details Selective high k dielectrics removal Selective high k dielectrics removal

2003-07-29

2004-11-16

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S307000

Reexamination Certificate

active

06818516

ABSTRACT:

FIELD
This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to forming integrated circuits with advanced dielectric materials.
BACKGROUND
Silicon dioxide has typically been used as the dielectric material between the electrically conductive gate electrode, often formed of polysilicon, and the semiconducting channel of a transistor, which is typically formed of silicon. Silicon dioxide has provided adequately high capacitance for gate insulation in the past, with devices having gate geometries of about 130 nanometers and greater. However, with the ever increasing demands of scaled-down device geometries and more densely populated integrated circuits, silicon oxide tends to no longer be good enough for the gate insulation layer.
Current transistor geometries use a gate insulation layer of silicon dioxide that is about twelve to sixteen angstroms thick, or the thickness of about six to ten individual silicon atoms. The silicon dioxide layer gates the electrons through the channel, controlling the flow of electricity across the transistor. However, when the transistor is reduced in size, the silicon dioxide gate insulation layer is also proportionally thinned. As gate lengths decrease from one hundred and thirty nanometers to ninety, sixty-five, and even thirty nanometers, the thickness of the silicon oxide gate will be reduced to less than ten angstroms, or to about three monolayers.
Unfortunately, once the gate insulation layer is reduced to less than about twenty angstroms, the silicon dioxide is no longer able to provide effective insulation from the effects of quantum tunneling currents, and the transistor tends to exhibit relatively high leakage.
Thus, the integrated circuit fabrication industry is searching for gate insulator materials with a low equivalent oxide thickness that mimics the electrical properties of very thin silicon dioxide, while providing a thicker physical layer over the channel to prevent quantum-mechanical tunneling. New materials in the form of oxides of heavy and rare earth metals, with higher dielectric constants and higher capacitances have been investigated with some promising results, including HfSiON, ZrO
2
, HfO
2
, HfON, La
2
O3, CeO
2
, Na
2
O
3
, Sm
2
O
3
, Eu
2
O
3
, Gd
2
O
3
, Tb
2
O
3
, Dy
2
O
3
, Ho
2
O
3
, Er
2
O
3
, Tm
2
O
3
, Yb
2
O
3
, Lu
2
O
3
.
However, these so called high k materials have other problems associated with their use. For example, they do not easily form volatile compounds and are relatively difficult to remove by either dry etching or wet etching. Dry etching has been attempted with ion milling or bombardment and sputtering with the use of argon or other inert ions. However, the process is time consuming and can cause extensive damage to the surrounding structures, such as the polysilicon gate electrode. The necessarily extended use of plasma as an etch tends to increase the plasma damage to the substrate itself, as well as to other structures.
There is a need, therefore, for a method whereby such high k materials can be patterned and etched without unduly damaging the surrounding structures that are formed in a conventional CMOS process flow.
SUMMARY
The above and other needs are met by a method of forming a gate structure in an integrated circuit on a substrate. A high k layer is formed on the substrate, and a gate electrode layer is formed on the high k layer. The gate electrode layer is the patterned. LDD regions are formed using an ion implantation process, thereby creating damaged portions of the high k layer. A first portion of the damaged portions of the high k layer are removed, thereby defining a gate structure, and leaving remaining portions of the damaged portions of the high k layer. Sidewall spacers are formed adjacent the gate structure. Source/drain regions are formed using an ion implantation process, thereby further damaging the remaining portions of the damaged portions of the high k layer. The remaining portions of the damaged portions of the high k layer are then removed.
In this manner, two different ion implantation processes are used to damage the high k layer, which enables it to be more readily and completely removed. However, special ion implantation processes are not required. Rather, the standard LDD and source/drain implantation processes are used, and the high k layer is thus removed by an etch following each of these two processes. Studies indicate that only as much as about three percent of the high-k layer remains after these two ion implantation processes and etch processes, which is an insufficient amount to substantially and detrimentally effect the integrated circuit.
Because the damaged high k material etches at a much faster rate than does the undamaged high k material, this process advantageously makes use of an etch that can proceed at an acceptably high etch rate. The higher the degree of crystallinity in the undamaged portions of the high k layer, the greater the etch differential between undamaged portions of the high k layer, such as in the gate structure, and the damaged portions of the high k layer. Thus, the etch of the high k layer is extremely anisotropic, tending only to appreciably remove those portions of the high k layer that have been damaged, and not undercutting the high k gate insulation layer within the gate structure to any appreciable extent.
In various preferred embodiments, the high k layer is at least one of HfSiON, ZrO
2
, HfON, La
2
O
3
, CeO
2
, Na
2
O
3
, Sm
2
O
3
, Eu
2
O
3
, Gd
2
O
3
, Tb
2
O
3
, Dy
2
O
3
, Ho
2
O
3
, Er
2
O
3
, Tm
2
O
3
, Yb
2
O
3
, Lu
2
O
3
, and most preferably hafnium dioxide. The LDD implanted species is preferably arsenic. Preferably, the LDD ion implantation is conducted at a dopant level of about 6(10)
13
atoms per square centimeter and at an energy of about eighty thousand electron volts. The first portion of the damaged portions of the high k layer is preferably removed using a solution of hydrofluoric acid. Preferably, the source/drain implanted species comprises arsenic. The source/drain ion implantation is preferably conducted at a dopant level of about 3(10)
15
atoms per square centimeter and at an energy of about forty thousand electron volts. Preferably, the remaining portions of the damaged portions of the high k layer are removed using a solution of hydrofluoric acid. There is preferably an additional step of forming a base interface layer on the substrate prior to the step of forming the high k layer. The high k layer is preferably formed using at least one of a metallorganic chemical vapor deposition process, an atomic layer deposition process, and a physical vapor deposition process. The gate electrode layer is preferably formed of at least one of polycrystalline silicon and polycrystalline germanium.


REFERENCES:
patent: 6063698 (2000-05-01), Tseng et al.
patent: 6303418 (2001-10-01), Cha et al.
patent: 6455330 (2002-09-01), Yao et al.
patent: 6656852 (2003-12-01), Rotondaro et al.

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