Selective formation of hydrogen rich PECVD silicon nitride...

Details Selective formation of hydrogen rich PECVD silicon nitride... Selective formation of hydrogen rich PECVD silicon nitride...

2000-01-18

2002-04-16

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S223000, C438S230000, C438S233000, C438S279000

Reexamination Certificate

active

06372569

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to formation of NMOS and PMOS transistor semiconductor devices, and more specifically to forming SiN etch stop layers over PMOS and NMOS semiconductor devices.
BACKGROUND OF THE INVENTION
Salicide is a common process in semiconductor device manufacturing to lower the sheet resistance of polysilicon gates. Silicides are silicon-metal structures and salicides are self-aligned suicides. However, as technology improves, new processes are needed to enhance the performance of semiconductor transistors.
U.S. Pat. No. 5,897,372 to Howard describes the use of silicon-rich silicon nitride as a protective layer in a self-aligning etch.
U.S. Pat. No. 5,807,779 to Liaw describes a process for fabricating metal-oxide semiconductor field effect transistors (MOSFETs) using a local interconnect structure and silicon nitride capped, self-aligned contact openings.
U.S. Pat. No. 5,930,627 to Zhou et al. describes the use of silicon-enriched silicon oxynitride (SiON) as both an independent etch stop and as a cap layer and sidewall component over polysilicon gate electrodes in order to prevent insulator thinning and shorts caused by a misaligned contact mask.
U.S. Pat. No. 5,863,820 to Huang describes a process and structure wherein logic and memory share the same chip. A protective coating of oxide (RPO) is formed over the pedestals of the source/drain regions of the memory side allowing the salicide process to be selectively applied to the memory side. While the logic side is protected, the self-aligned contact (SAC) process is applied to the memory side.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of forming H
2
-rich PECVD nitride films over PMOS and NMOS transistor semiconductor structures without detrimentally affecting the PMOS transistors.
Another object of the present invention is to provide a method of forming a PMOS AND NMOS semiconductor structure with improvements in NMOS transistor's margins without any detrimental impact on the PMOS transistor.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically a semiconductor structure having at least one PMOS transistor and one NMOS transistor formed therein is provided. The PMOS and NMOS transistors each have source/drain regions, a gate, and salicide contact regions. A liner is deposited over the semiconductor structure and the PMOS and NMOS transistors. An H
2
-rich PECVD silicon nitride layer is deposited over the undoped silicate glass layer and over the PMOS and NMOS transistors. The H
2
-rich PECVD silicon nitride layer is patterned, etched, and removed from over the PMOS transistor. An inter-level dielectric (ILD) layer is formed over the structure. The ILD layer is densified whereby hydrogen diffuses from the H
2
-rich PECVD silicon nitride layer overlying the NMOS transistor into the source/drain of the NMOS transistor.


REFERENCES:
patent: 5807779 (1998-09-01), Liaw
patent: 5863820 (1999-01-01), Huang
patent: 5897372 (1999-04-01), Howard
patent: 5930627 (1999-07-01), Zhou et al.
patent: 6261891 (2001-07-01), Cheng et al.
patent: 6277683 (2001-08-01), Pradeep et al.

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