Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-30
2003-04-15
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S478000, C438S585000, C438S770000
Reexamination Certificate
active
06548335
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing semiconductor devices, e.g., MOS-type transistors and integrated circuits comprising such devices exhibiting improved quality, e.g., improved channel carrier mobility, high transistor drive current and improved circuit performance. The present invention is particularly applicable in fabricating high-density integration semiconductor devices with a design rule less than about 0.18 micron, e.g., about 0.15 micron and under.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultralarge-scale integration (ULSI) semiconductor devices require a design rule of 0.18 micron and below, e.g., about 0.15 micron and below, increased transistor and circuit speeds, high reliability and quality, and increased manufacturing throughput for economic competitiveness. The reduction of design rules to 0.18 micron and below challenges the limitations of conventional semiconductor manufacturing techniques.
High performance microprocessor applications require rapid speed of semiconductor circuitry. A limitation on the drive current of a transistor stems from reduced carrier mobility, i.e., electron or hole mobility, in the channel region of a MOSFET. The reduction of channel carrier mobility reduces the drive current and performance of the circuit.
Accordingly, there exists a need for efficient, cost-effective methodology for manufacturing MOS devices exhibiting improved transistor drive current and circuit performance. There exists a particular need for such methodology for fabricating semiconductor devices having a design rule less than about 0.15 micron and under that is compatible with conventional process flow for improved efficiency and increased manufacturing throughput.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is an improved method for forming semiconductor devices with increased channel carrier mobility, improved transistor drive current and improved circuit performance.
Additional advantages and other features of the present invention will be set forth in the description that follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a field dielectric region isolating an active region in a semiconductor substrate; growing a layer of semiconductor material in the active region by selective epitaxy; thermally oxidizing a surface of the epitaxially grown layer to form a gate oxide layer; and depositing a gate electrode layer on the gate oxide layer.
Embodiments of the present invention comprise forming a silicon oxide isolation region on a silicon semiconductor substrate, depositing silicon by selective epitaxy on the active region by a mechanism which is predominantly monolayer by monolayer; thermally oxidizing the surface of the epitaxially deposited silicon to form a gate oxide layer having a substantially smooth surface and forming a gate electrode layer on the gate oxide layer. Embodiments of the present invention also comprise growing the layer of silicon by selective epitaxy to a thickness of about 5 Å to about 10 Å and forming the gate oxide layer at a thickness of about 3Å to less than about 20 Å.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawing and description art to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 5428234 (1995-06-01), Sumi
patent: 6064077 (2000-05-01), Sandaresan
patent: 6429061 (2002-08-01), Rim
patent: 07176742 (1995-07-01), None
patent: WO 97/28560 (1997-08-01), None
Silicon Processing For The VLSI Era, vol. 1, Process Technology, Stanley Wolf, Ph.D., Richard N. Tauber, Ph.D., pp. 155-156.
Huster Carl Robert
Luning Scott
Riccobene Concetta
Lytle Craig P.
Smith Matthew
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