Selective electroless-plated copper metallization

Details Selective electroless-plated copper metallization Selective electroless-plated copper metallization

2007-05-01

2007-05-01

Nguyen, Ha (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S678000, C438S638000, C257SE21582, C257SE21583, C257SE21584

Reexamination Certificate

active

09483881

ABSTRACT:
Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate. This method includes depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on a substrate. The seed layer is deposited to a thickness of less than 15 nanometers (nm). A photolithography technique is used to define a number of via holes above the seed layer. In one embodiment, using a photolithography technique includes forming a patterned photoresist layer to define the number of via holes above the seed layer. A layer of copper is deposited over the seed layer using electroless plating filling the number of via holes to a top surface of the patterned photoresist layer. The method can be repeated any number of times depositing a second seed layer, depositing another patterned photoresist layer defining a number of conductor line openings above the second seed layer, and forming a second layer of copper using electroless plating which fills the number of conductor line openings to a top surface of the second patterned photoresist layer. The photoresist layers along with the seed layers in other regions can then be removed, such as by oxygen plasma etching, such that a chemical mechanical planarization process is avoided. Structures formed by this novel process are similarly included within the scope of the present invention.

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