Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-08-28
2007-08-28
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C257SE29130
Reexamination Certificate
active
10857931
ABSTRACT:
Multiple semiconductor devices are formed with different threshold voltages. According to one exemplary implementation, first and second semiconductor devices are formed and doped differently, resulting in different threshold voltages for the first and second semiconductor devices.
REFERENCES:
patent: 4319395 (1982-03-01), Lund et al.
patent: 4399605 (1983-08-01), Dash et al.
patent: 5942786 (1999-08-01), Sheu et al.
patent: 6171910 (2001-01-01), Hobbs et al.
patent: 6319781 (2001-11-01), Lee et al.
patent: 6391750 (2002-05-01), Chen et al.
patent: 6451693 (2002-09-01), Woo et al.
patent: 6589836 (2003-07-01), Wang et al.
patent: 6657259 (2003-12-01), Fried et al.
patent: 6677204 (2004-01-01), Cleeves et al.
patent: 6800905 (2004-10-01), Fried et al.
patent: 6803631 (2004-10-01), Dakshina-Murthy et al.
patent: 6846734 (2005-01-01), Amos et al.
patent: 2001/0045589 (2001-11-01), Takeda et al.
patent: 2002/0088971 (2002-07-01), Tezuka et al.
patent: 2004/0038464 (2004-02-01), Fried et al.
patent: 2004/0048424 (2004-03-01), Wu et al.
patent: 2004/0063286 (2004-04-01), Kim et al.
patent: 2004/0195628 (2004-10-01), Wu et al.
Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Co-pending U.S. Appl. No. 10/614,001; by Shibly S. Ahmend et al; filed Jul. 8, 2003; 20 page specification, 8 sheets of drawings.
Co-pending U.S. Appl. No. 10/674,520; by Haihong Wang et al.; filed Oct. 1, 2003; 16 page specification; 19 sheets of drawings.
Ahmed Shibly S.
Wang Haihong
Yu Bin
Advanced Micro Devices , Inc.
Harrity & Snyder LLP
Tsai H. Jey
LandOfFree
Selective channel implantation for forming semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Selective channel implantation for forming semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective channel implantation for forming semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3868896