Selection of optimal quantization direction for given...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S292000

Reexamination Certificate

active

07091078

ABSTRACT:
A technique for selecting an optimal quantization direction for a given transport direction in a semiconductor device such as a field effect transistor (FET), a method for preparing a wafer for fabricating such a semiconductor device, and the semiconductor device fabricated by the method. A switching time is calculated for different candidate quantization directions, and for a given current transport direction. The quantization direction that results in the lowest switching time is then determined. In a specific example, Ge nFET performance is enhanced by 12% using the [1 1 0] and [{overscore (4)} 4 21] crystallographic directions for transport and quantization, respectively. Quantization in the [{overscore (1)} 1 0] direction was previously considered optimal.

REFERENCES:
patent: 2001/0030354 (2001-10-01), Shimizu et al.
Baron, F. A. et al. “Manipulating the L-Valley ElectronGFactor in Si-Ge Heterostructures.”Phys. Rev. B68, 195306 (2003).
Choi, Yang-Kyu et al. “Sub-20nm CMOS FinFET Technologies.”IEEE(2001).
Low, Tony et al. “Investigation of Performance Limits of Germanium Double-Gates MOSFETs.”IEEE(2003).
Laux, S. E. et al. “Analysis of Quantum Ballistic Electron Transport in Ultrasmall Silicon Devices Including Space-Charge and Geometric Effects.”J. Appl. Phys.95, 10 5545 (2004).
Guarini, K. W. et al. “Triple-Self-Aligned, Planar Double-Gate MOSFETs: Devices and Circuits.”IEEE(2001).
Na, M. H. et al. “The Effective Drive Current in CMOS Inverters.”IEEE(2002).

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