Selectable clocking synchronization of a parallel-to-serial...

Details Selectable clocking synchronization of a parallel-to-serial... Selectable clocking synchronization of a parallel-to-serial...

2005-08-02

2005-08-02

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C710S071000, C375S354000

Reexamination Certificate

active

06925575

ABSTRACT:
A technique includes providing a first clock signal to a parallel-to-serial data conversion circuit and providing a second clock signal to a memory storing data for conversion by the conversion circuit. One of the first and second clock signals is selectively synchronized to a reference clock signal.

REFERENCES:
patent: 5319339 (1994-06-01), Leupold
patent: 5319369 (1994-06-01), Majos et al.
patent: 5369376 (1994-11-01), Leblebicioglu
patent: 5563594 (1996-10-01), Ford et al.
patent: 5896391 (1999-04-01), Solheim et al.
patent: 6188286 (2001-02-01), Hogl et al.
patent: 6252465 (2001-06-01), Katoh
patent: 6667663 (2003-12-01), Ozawa
patent: 6828864 (2004-12-01), Maxim et al.
patent: 6845074 (2005-01-01), Fujita

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