Segmented read line circuit particularly useful for multi-port s

Details Segmented read line circuit particularly useful for multi-port s Segmented read line circuit particularly useful for multi-port s

1995-09-07

1997-07-08

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523005, 365 63, G11C 700

Patent

active

056468938

ABSTRACT:
A read line for a column of memory cells within an array is divided into a first read line segment, a first read buffer, and a second read line segment. Both the first and second read line segments occupy a single wiring channel. When reading a memory cell connected to the first read line segment, the level of the first read line segment is sensed by the first read buffer and conveyed to a column read output node by way of the second read line segment and an associated second read buffer. Alternatively, when reading a memory cell connected to the second read line segment, the first read buffer is disabled, thus adopting a high impedance output, and the level of the second read line segment is sensed by the second read buffer and conveyed to the column read output node. Each of the first and second read line segments have less capacitive loading than a single read line, which results in lower power and faster read access times. Further, when reading a memory cell coupled to the second read line segment, the first read line segment remains in a precharged state, conserving power even more. Consequently, when used as part of a multiport register file within a processor, power is reduced by implementing registers having a high frequency of reference as memory cells coupled to the second read line segment.

REFERENCES:
patent: 4532613 (1985-07-01), Takemae et al.
patent: 5422857 (1995-06-01), Ninomiya et al.
Toshihiko Hirose, et al., "A 20-ns 4-Mb CMOS SRAM with Hierarchical Word Decoding Architecture", pp. 1068-1074, IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990.

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