Segmented column memory device voltage steering technique

Details Segmented column memory device voltage steering technique Segmented column memory device voltage steering technique

1999-05-26

2001-02-27

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S185330

Reexamination Certificate

active

06195295

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to electronically programmable memories and particularly flash EEPROM memories.
BACKGROUND OF THE INVENTION
As used herein, the term “high voltage” refers to voltages of nominally more than 5 volts; the term “low voltage” refers to voltages of 5 volts or less, being typically 3.3 volts or less. The term “high voltage transistor” refers to a transistor designed to operate with a minimum of degradation at a high voltage (e.g., a thick-oxide transistor); and the term “low voltage transistor” refers to a transistor designed to operate only at a low voltage (e.g., a low-voltage CMOS transistor).
The use of embedded flash EEPROM (Electronically Erasable Programmable Read Only Memory) in cellular phones, answering machines, cordless phones and other devices containing silicon integrated circuits is increasing. Current generation flash EEPROMs require the use of circuitry and thick-oxide transistors capable of handling high voltages (e.g., typically 7 volts) in the critical read column precharge path for erasing and programming (writing) the flash memory cells because the columns must be raised to high voltages during erase and programming operations (hereinafter referred to collectively as “high voltage memory operations”). However, the use of high voltage transistors in EEPROMs has negative effects on performance. For instance, high voltage transistors operated at high voltages are subject to parameter degradation and are inherently less reliable than low voltage core CMOS transistors operated at lower voltages (e.g., less than 5 volts, typically about 3 volts). Read precharge and cycle times also are increased when high voltage transistors are used in the critical read column precharge path because of their significantly lower gain (typically less than one-half the gain of low voltage core CMOS transistors).
FIG. 1
illustrates a typical EEPROM circuit
10
of the prior art.
FIG. 1
shows a flash EEPROM memory array
20
having N columns (C
1
, C
2
, . . . C
N
) and M rows (R
1
, R
2
, . . . R
M
), an associated on-pitch sense amplifier block
30
, column select transistor block
40
, high voltage column precharge transistor block
50
, and write/erase data transfer gate block
60
.
Each memory cell in memory array
20
comprises a floating gate transistor in which the drain terminal is coupled to the associated column, the gate terminal is coupled to the associated row, and the source terminal is coupled to a source. In essence, a floating gate transistor comprises a first gate, the floating gate, positioned above the current channel of the transistor and separated therefrom by a layer of insulation (e.g., oxide) and a second gate, the fixed gate, positioned above the first gate and separated therefrom by another layer of insulation. The fixed gate is directly coupled to the gate terminal of the transistor. Both stacked gate and split gate designs are known in the art.
The column precharge transistor block
50
comprises a thick oxide, high voltage transistors
51
(
1
),
51
(
2
), . . .
51
(N) coupled to each column, respectively.
As is known in the art, in order to read a flash memory cell, the column associated with that cell must be precharged to a specific voltage, e.g., 1 volt. If that cell has been written to, that is, if it stores a logic 1, then the transistor comprising that cell will remain off when the corresponding row is asserted and will not discharge the voltage that was placed on the column through the precharge transistor. If, on the other hand, the memory cell is erased, that is, if it stores a digital 0, then that cell will be turned on when the corresponding row is asserted, thus driving the column to ground through the source-drain path of the memory cell transistor.
The sense amplifiers
30
(
1
),
30
(
2
), . . .
30
(m) amplify the column voltage as set by the cell on that column that is being read to produce an output.
As is known in the art, when erasing a flash EEPROM memory array, the columns (drain terminals of the memory cells) are raised to a high voltage, typically 7 volts, while the rows (gate terminals), R
1
, R
2
, . . . ,R
M
, are kept at ground (0 volts) or reduced to a negative potential below ground. The source is commonly open circuited for erasing. The high gate to drain voltage differential causes electron tunneling from the drain of the transistor to the floating gate, raising the nominal potential of the floating gate. Enough electron tunneling is allowed to occur to raise the nominal potential of the floating gate to a point at which it will rise above the transistor's threshold current when the corresponding row is asserted (i.e., when the fixed gate is raised to a logic high level, such as 3.3 volts). This will cause the transistor to conduct when the corresponding row is asserted (for reading that cell), thus driving the corresponding column to ground.
When writing a flash EEPROM memory array
20
, columns (gates) associated with cells to be written (i.e., that are to store a digital
1
) are raised to a high potential, typically 7 volts, as are the rows (drains) associated with the cells to be written. The source terminals are grounded. Other columns associated with cells along the same row that are not being written remain at ground. This condition causes hot electron injection from the current channel to the floating gate, thus lowering the nominal potential of the floating gate. Enough electron injection is allowed to occur to lower the nominal potential of the floating gate to a point at which, even when the gate terminal is raised to 3 volts, i.e., when the corresponding row is asserted, the floating gate will still be below the threshold voltage such that the transistor will not conduct. Accordingly, the column will not be discharged and the cell will be read as logic 1.
It can, therefore, be seen that, when erasing or writing a cell, it is necessary to raise the associated column to a high voltage level. Accordingly, the column precharge transistors, having their drain terminal coupled to the columns, must be high-voltage, thick oxide, transistors in order to handle the high voltage. During erase and write operations, the gates of precharge transistors
51
(
1
),
51
(
2
), . . .
51
(N) are at ground (0 volts) along PRECHARGE input
52
. This results in a high gate-to-drain potential (e.g., 7 volts) for each transistor, which is easily withstood by the high voltage transistors, but which would destroy low voltage core CMOS transistors.
With reference to the first column C
1
in
FIG. 1
, the method and circuitry of the prior art will be described. For erase and write operations, prior to applying high voltage to inputs D
1
and RC
1
, the precharge input
52
must be set to ground to prevent conduction through the precharge transistor
51
(
1
) within precharge block
50
. Also, in preparation for applying high voltage to the first column C
1
for writing/erasing, a high voltage, typically 7 volts, is applied to the data input D
1
and the read control input RC
1
of the write/erase data transfer gate block
60
. This sets up the data, but blocks conduction through devices M
7
and M
8
.
If the entire memory is being erased, all data input terminals D
1
, . . . D
n
receive the high voltage. For programming, however, only the column containing the cell or cells being programmed are charged.
Then, the write or erase is initiated by lowering the read control input RC
1
, thus allowing the high voltage applied to data input D
1
to be transferred onto column C
1
. Specifically, lowering the read control input RC
1
, turns on devices M
7
and M
8
, passing the high voltage from data input D
1
onto the column.
If the operation is a write, then, for those columns associated with cells not to be written, but along the same row as other cells being written, their voltage is kept at ground by keeping their data inputs (i.e., D
1
, D
2
, . . . D
N
) at ground.
The column select transistor block
40
and sense amplifier block
30
are used for reading the flash memory. Parti

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