SEG combined with tilt side implant process

Details SEG combined with tilt side implant process SEG combined with tilt side implant process

2000-01-31

2002-02-26

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S630000

Reexamination Certificate

active

06350656

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an integrated circuits fabrication, and more particularly to a SEG (selective epitaxial growth) method combined with tilt SDE (source/drain extension) implant.
2. Description of the Prior Art
As MOS (Metal-oxide-semiconductor) devices scaled down to sub 0.1 micron, in order to maintain the performance gain and device characteristics, some aggressive modules have been proposed, such as SEG (selective epitaxial growth) on silicon substrate and polysilicon.
Referring to
FIG. 1
, a cross-sectional view of a conventional MOS device with SEG is shown there. A well
110
between two isolation regions
120
is in a substrate
100
, in which isolation regions
120
are shallow trench isolations. Source/drain regions
112
on the surface of an active area are separated by a gate electrode
116
, and SDE (source/drain extension) regions
114
are underlying a spacer
122
near gate electrode
116
. Regions
118
on the source/drain regions
112
and gate
116
are formed by SEG.
The method for forming the MOS device in
FIG. 1
comprises the steps of first providing the substrate
100
with the active area defined therein and forming shallow trench isolation regions
120
besides the active area. Then, the well
110
is formed by implantation in the active area. Next, a gate oxide layer and the gate electrode
116
are successively formed on the active area. Then, the SDE regions
114
are formed in the active area by using gate
116
as a mask. After that, the spacers
112
are formed on the two sides of the gate
116
. Next, the SEG regions
118
are formed on the source/drain regions
112
and gate
116
, and the source/drain regions
112
are formed sequentially by using implantation. The follow-up process that have been carried out after the formation of the MOS device are salicide (self-aligned silicide) process and the backend process.
Conventional process is very complicated, because the formulation of SDE regions and source/drain regions needs two implantation steps and two lithography steps (one for NMOS and another for PMOS). Moreover, under such process, the ultra shallow junction can not be reached.
SUMMARY OF THE INVENTION
In accordance with the present invention, a SEG combined with tilt SDE implant method is provided for forming a MOS device that substantially reduces source/drain implantation and lithography steps, because SDE and source/drain implant can be preformed in one step. Moreover, the MOS device can reach ultra shallow junction with the aid of SEG combined with tilt SDE implantation.
It is another object of this invention that the capacitance of the overlapping region between gate and drain can be adjust by the spacer width and the tilt angle for achieving a better performance.
It is a further object of this invention that SDE implant after the formation of the spacer can avoid the thermal cycle of spacer step for achieving ultra shallow junction and reducing the out diffusion of Boron.
In one embodiment, a SEG combined with tilt implant method for forming semiconductor device includes providing a substrate with an active area defined therein, and then forming shallow trench isolation regions around the active area. Then, a well is formed in the active area, and a gate electrode is subsequently formed on the active area. Next, spacers are formed on the sidewall of the gate electrode. As a key step of the invention, selective epitaxial growth regions are formed on the active area and the gate electrode, and then the active area is implanted with an angle to form source/drain regions beside the bottom edge of the gate electrode. Next, the source/drain regions are annealed such that the source/drain regions diffuse to the regions underlying the gate electrode. Then, the salicide process and backend processes are performed.


REFERENCES:
patent: 5217910 (1993-06-01), Shimizu et al.
patent: 5355006 (1994-10-01), Iguchi
patent: 5733792 (1998-03-01), Masuoka
patent: 5773347 (1998-06-01), Kimura et al.
patent: 5883418 (1999-03-01), Kimura
patent: 6037232 (2000-03-01), Wieczorek et al.

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