Secure exchange of information in electronic design automation

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C705S051000, C705S059000, C713S160000, C713S165000, C713S193000

Reexamination Certificate

active

10895485

ABSTRACT:
Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. For instance, the tool may be a physical verification tool capable of verifying whether any of the one or more integrated circuit layouts may violate one or more of the secured rules. An error report may be generated without revealing the secured rules.

REFERENCES:
patent: 5708709 (1998-01-01), Rose
patent: 5787169 (1998-07-01), Eldridge et al.
patent: 5966707 (1999-10-01), Van Huben et al.
patent: 5978476 (1999-11-01), Redman et al.
patent: 6006190 (1999-12-01), Baena-Arnaiz et al.
patent: 6012033 (2000-01-01), Vanden Berge
patent: 6118869 (2000-09-01), Kelem et al.
patent: 6256768 (2001-07-01), Igusa
patent: 6401230 (2002-06-01), Ahanessians et al.
patent: 6594799 (2003-07-01), Robertson et al.
patent: 6782511 (2004-08-01), Frank et al.
patent: 6904527 (2005-06-01), Parlour et al.
patent: 6976166 (2005-12-01), Herley et al.
patent: 6981153 (2005-12-01), Pang et al.
patent: 6999910 (2006-02-01), Koford et al.
patent: 7111258 (2006-09-01), Kato et al.
patent: 7127692 (2006-10-01), Hamlin
patent: 2002/0010681 (2002-01-01), Hillegass et al.
patent: 2002/0099947 (2002-07-01), Evans
patent: 2002/0107809 (2002-08-01), Biddle et al.
patent: 2002/0156757 (2002-10-01), Brown
patent: 2002/0184494 (2002-12-01), Awadalla
patent: 2003/0140255 (2003-07-01), Ricchetti et al.
patent: 2003/0149669 (2003-08-01), Howells et al.
patent: 2003/0182578 (2003-09-01), Wamock et al.
patent: 2003/0221116 (2003-11-01), Futoransky et al.
patent: 2004/0093397 (2004-05-01), Chiroglazov et al.
patent: 2004/0098391 (2004-05-01), Robertson et al.
patent: 2004/0221179 (2004-11-01), Seshadri
patent: 2004/0230841 (2004-11-01), Savini
patent: 2005/0092848 (2005-05-01), Beit-Grogger et al.
patent: 2006/0041502 (2006-02-01), Blair et al.
patent: 2006/0064383 (2006-03-01), Marking
patent: 2006/0069925 (2006-03-01), Nakai et al.
Sotiriou et al., “De-synchronization: asynchronous circuits from synchronous specifications”, Sep. 17-20, 2003, SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip], p. 165-168.
Seok-Bum et al., “A novel technology mapping method for AND/XOR expression”, May 16-19, 2003, Multiple-Valued Logic, 2003. Proceedings. 33rd International Symposium on, pp. 133-138.
International Search Report, Sep. 30, 2005, PCT/US2004/029679, 5 pages.
Written Opinion for PCT/US2004/029679, filed Sep. 10, 2004, 7 pages, date written Sep. 30,2005.
Ko et al., “A Novel Technology Mapping Method for AND/XOR Expressions,”Proceedings of the 33rdInternational Symposium on Multiple-Valued Logic, 2003.
“IEEE Standard for Verilog® Hardware Description Language,”IEEE Std. 1364-2005, pp. 467-541, Apr. 7, 2006.
“IEEE Standard for Verilog® Hardware Description Language,”IEEE Std. 1364-1995, 879 pages, Sep. 28, 2001.
Goering, “Open crypto tool standard danglesKEY TO IP,” 5 pages <http://www.eetimes.com/showArticle.jhtml?articleID=189401977>, Jun. 19, 2006.
Dauman, “An open IP encryption flow permits industry-wide interoperability,”Synplicity, Inc. White Paper, 8 pages, Jun. 2006.
Mehta, “Essential elements of a successful IP evaluation,”EETimes, 4 pages <http://www.eetimes.com/editorial/2000/insideip00009.html>, Sep. 20, 2006.
“HSPICE, The gold standard for accurate circuit simulation,”Synopsys Data Sheet, 4 pages, 2006.
“ESNUG,”Deepchip, 13 pages <http://www.deepchip.com/posts/0329.html#09>, Sep. 18, 2006.

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