Secure and dense SRAM cells in EDRAM technology

Details Secure and dense SRAM cells in EDRAM technology Secure and dense SRAM cells in EDRAM technology

2001-10-02

2003-01-14

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S149000

Reexamination Certificate

active

06507511

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to high capacity static random access memories and other types of integrated circuits formed at high integration density and, more particularly, to achieving high levels of immunity to soft errors in such memories.
2. Description of the Prior Art
Since the development of integrated circuits, the potential for reduced signal propagation time and increased functionality of individual chips as well as manufacturing economy has driven development of increases in integration density and scaling of individual circuit elements therein to smaller sizes. This incentive for scaling is particularly strong for memory devices which have approximately quadrupled in capacity every three years. However, such scaling of individual elements inevitably increases criticality of many aspects of operation such as operation at reduced voltages, susceptibility to noise, heat dissipation and the like.
Among other problems aggravated by scaling, particularly in memory structures, is the problem of soft errors due to the transit of alpha particles through a memory cell. Alpha particles are substantially unavoidable in the environment and their relatively high energy causes ionization which can introduce charge into the circuit in an unpredictable manner but without causing damage to the circuit element or impairing its function. In practical effect in a memory cell, the disturbance of charge may be sufficiently great that the storage or logic state of the cell will be changed and the data corrupted but the cell will be capable of functioning correctly when new data is stored. For this reason, such errors are referred to as “soft” as opposed to “hard errors” such as a failed transistor or a wiring defect which prevents correct functioning of the circuit.
Scaling causes increased susceptibility to soft errors because it decreases the amount of charge required to induce a soft error through a number of mechanisms. That is, the amount of charge developed by the traverse of a given alpha particle through a circuit is highly variable depending on a number of factors such as the energy of the alpha particle, its trajectory through the circuit and the like. Therefore, not all incident alpha particles will induce a soft error. However, reduction of the amount of charge necessary to induce a soft error (or, for that matter, an intended change of logic state) can be considered as a reduction in the stability of a memory cell and, for a given distribution of energies and trajectories of a given flux of alpha particles, the number of soft errors will increase as the critical amount of charge that will induce a soft error, Q
crit
, decreases. The amount of charge that can upset a memory cell of a given type has been decreasing by about one-half per generation; more or less proportionally to the decrease in circuit element and memory cell dimensions.
Further, numbers of soft errors per chip are increased by increased integration density. Substantially increased total soft error rates of about 50K ppm/khr/chip (with some significant differences between low to high and high to low transition errors) are projected for 8 Megabyte memories currently being designed and manufactured having a cell size of about 2.5 to 5 &mgr;m
2
. That is, while soft errors are relatively rare and current memory cell designs are highly reliable and stable, such a memory can now be expected to experience a soft error, on average, every one to two months and may vary significantly (e.g. may double or more) with the logic state stored. (By way of comparison, soft error rates were negligible in SRAM designs of only a few generations previous to current designs.) Given the amount of memory generally associated with modern processors and the fact that any soft error corrupts data or an application program, it can be readily appreciated that some provision must be made for correction or avoidance of soft errors in order to support acceptable processor performance.
Unfortunately, most approaches to soft error correction compromise performance, especially processing speed, and/or integration density. That is, error detection/correction circuits or redundant designs that have been used in the past to alleviate the problem of soft errors are either very expensive and/or very slow. For example, some designs duplicate the cell array and, upon read out, picks the data with correct parity rather than performing a slow and complicated error detection and correction procedure even though such an approach more than doubles cost, limits usable memory capacity per chip and increases access time.
It has also been proposed to harden memories against soft errors by using triple well designs and/or to use B11-enriched BPSG processes. However, this approach does not provide protection against soft errors and, in fact, would provide only a marginal (10-50%) reduction in soft error rates while increasing production costs significantly. The addition of further circuit elements such as resistor-capacitor circuits to increase stability of memory cells by reducing alpha particle induced transients have been proposed but would result in much larger cell size and much slower access time as well as increasing power consumption and heat dissipation requirements. Neither of these proposals would avoid a need for error detection and correction circuitry which is slow and complicated; reducing overall processor performance.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a memory cell design having reduced susceptibility to soft errors without compromise of either cell size or access time and without significantly increasing manufacturing cost or reducing manufacturing yield.
It is another object of the present invention to provide a technique of greatly reducing susceptibility to soft errors that can be implemented in arbitrary and/or existing memory cell designs.
In order to accomplish these and other objects of the invention, a circuit integrated on a chip is provided including an active digital circuit having a storage node, a deep trench capacitor formed under and having an electrode connected to a connection of the storage node.
In accordance with another aspect of the invention, an integrated circuit is provided including a circuit having a storage node, an impurity well region and a deep trench capacitor connected to said storage node, said deep trench capacitor including a connection to a plate of the deep trench capacitor being formed by the impurity well region.
In accordance with a further aspect of the invention, a method for making an integrated circuit is provided comprising steps of forming a deep trench capacitor and a circuit having a storage node overlying and connected to the capacitor.


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