Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2001-04-17
2002-10-15
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S204000, C365S202000, C365S189070
Reexamination Certificate
active
06466497
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to digital electronic circuits, specifically, digital circuits adapted for use with computer systems. More particularly, the present invention relates to a method of precharging sense amplifiers, such as those used with register files of high-speed microprocessors.
2. Description of the Related Art
The basic structure of a conventional computer system includes a central processing unit (CPU) or processor which is connected to several peripheral devices, including input/output (I/O) devices such as a display monitor and keyboard for the user interface, a permanent memory device (such as a hard disk or floppy diskette) for storing the computer's operating system and user programs, and a temporary memory device (such as random-access memory or RAM) that is used by the processor to carry out program instructions. The processor communicates with the peripheral devices by various means, including a bus or a direct channel. A computer system may have many additional components such as serial, parallel, and universal serial bus (USB) ports for connection to, e.g., modems or printers.
A conventional processor configuration includes several execution units (such as fixed-point and floating-point units) and various registers for holding operand data and program instructions, as well as units adapted to route information between the other components. For example, a typical processor includes a bus interface unit (BIU) which controls the flow of data between the processor and the remainder of the data-processing system. The bus interface unit is often connected to both a data cache and an instruction cache which are “on-board”, that is, fabricated on the same semiconductor wafer as the processor core. The instruction cache supplies instructions to a branch unit which determines what sequence of instructions is appropriate given the contents of certain general-purpose registers (GPRs), special purpose registers (SPRs), or floating-point registers (FPRs), the availability of a load/store unit (LSU) and the fixed-point and floating-point execution units, and the nature of the instructions themselves. The branch unit may forward the ordered instructions to a dispatch unit, which issues the individual instructions to the appropriate execution unit (i.e., the load/store unit, fixed-point execution unit, or floating-point execution unit).
The contents of a register file are physically read using an array of sense amplifiers. Sense amplifiers can generally be either single-ended or differential. In a traditional differential sense amplifier array, each register or cell has a pair of outputs, viz., a true line (T) and a complementary line (C), which together constitute the “bitline.” These lines are connected to the sense amplifier whose output is read by one of the execution units of the processor. During an evaluation cycle, a differential signal is developed between the pair of output lines. In other words, one of the T/C lines is in a high state, while the other is in a low state. Use of two such outputs and a sense amplifier simplifies evaluation since it does not require that the lines have a precise voltage, but rather only requires that there be a discernable difference between the two lines, i.e., one is higher than the other. It is also necessary to restore (precharge) the differential T/C pair after or before each access of the cell, i.e., raise each line to the high state (V
dd
).
It is also necessary to precharge the bitline in a single-ended sense amplifier. As shown in
FIG. 1
, a typical single-ended sense amplifier
1
has a single input
2
(the read bitline sa_in). The read cycle is initiated with the bitline being precharged and then conditionally being pulled low by the new memory location. During the evaluate phase, a small drop in sa_in is detected using inverter
3
(INV
1
) and transistor
4
(TN
2
) to produce full-rail swing at node
5
(lin), which is the input to another inverter
6
(I
3
) that provides the output
7
(sa_out) of the sense amplifier.
Register files used in high-end microprocessors as on-chip memory may have multiple read and write access ports and large numbers of entries. This construction results in a very large size of the register file, and the register file access lines (the bitlines) end up being very long. Reading the content of the register file through long and highly-loaded read bitlines is usually a processing bottleneck in high-speed register file designs.
To improve the read access timing, oftentimes a small transition in the read bitline voltage is sensed using a sense amplifier, instead of a full swing in the bitline voltage. Both differential as well as single-ended schemes based on a sense amplifier can be used and the trade-offs involved with theses are well-known. However, for multi-ported register files, single-ended sensing schemes result in less on-chip area and usually better timing (speed). For a single-ended sense amplifier scheme such as that illustrated in
FIG. 1
, during the precharge phase of the clock cycle, the bitline is precharged to a voltage level usually half of the supply voltage (V
dd
). During the evaluate phase of the clock cycle, the read bitline is conditionally discharged to a lower voltage based on the content of the register file. The sense amplifier amplifies this small variation in the read bitline at the input to produce a full-rail transition at the output.
The difference in the precharged voltage and the lower voltage at which the sense amplifier triggers is defined as the “noise margin.” This margin is the variation in read bitline voltage (due to electrical noise) which the sense amplifier can tolerate without falsely triggering. There is a direct trade-off between the speed of a sense amplifier and its noise margin. If the bitline is not precharged at the original voltage level after evaluating the read bitline, the noise margin is reduced. For large register files, it has been difficult or impossible to completely precharge the long read bitlines at high clock frequencies (e.g., one gigahertz or more).
In
FIG. 1
, during the precharge phase, which is enabled via the precharge line
8
(prec_
1
), the bitline is pulled higher turning off inverter
3
(INV
1
). The bitline continues to be precharged after INV
1
turns off until it reaches the threshold set by inverter
9
(INV
2
). This additional precharge provides the noise margin for the single-ended sense amplifier. Noise margin of the single-ended sense amplifier is defined as the drop in the sense amplifier input voltage (bitline) from the precharge level to the level where it triggers. Any noise in the bitline of this magnitude will falsely trigger the sense amplifier. The relative sizes of INV
1
and INV
2
can be adjusted for a desired noise margin; however, the speed at which the sense amplifier can be reliably used is affected by this. For example, if a read bitline is not completely precharged at a particular frequency then, it may have a voltage of only 452 mV at the end of the precharge phase as compared to an original precharge value of 464 mV. The noise margin is reduced by this difference. The sense amplifier detecting inverter INV
1
cannot completely detect this state of the bitline, and its output (csgate) does not completely switch. The result is a bump in the csgate node voltage in the next evaluate phase, and any noise on the bitline can falsely trigger the sense amplifier.
By increasing the cycle time (i.e., reducing the speed) the bitline can completely precharge and the original noise margin can be restored. However, at higher frequency the noise margin is sacrificed. Also, since the resistor-capacitor (RC) load of the long bitline is a limiting factor in precharging, adjusting the transistor sizes in the sense amplifier does not solve the problem. It would, therefore, be desirable to devise an improved method of precharging a sense amplifier which improves the noise margin of the sense amplifier, and still allows it to funct
Desai Shaishav A.
Gopaladhine Srinivasa
Mehta Anup S.
Hamilton & Terrile LLP
Nguyen Viet Q.
Sun Microsystems Inc.
Terrile Stephen A.
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