Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2007-04-24
2007-04-24
Estrada, Michelle (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S627000, C438S628000, C438S637000, C438S643000, C438S644000, C257SE23116, C257SE21579
Reexamination Certificate
active
10728774
ABSTRACT:
Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k material.
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Okada Lynne A.
Tran Minh Quoc
Wang Fei
You Lu
Advanced Micro Devices , Inc.
Estrada Michelle
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