Sealing porous structures

Details Sealing porous structures Sealing porous structures

2002-11-22

2004-07-06

Dang, Puch T. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S640000

Reexamination Certificate

active

06759325

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to forming protective layers prior to alternating layer deposition (ALD). More particularly, the invention relates to forming sealing layers prior to high conformality ALD layers over porous layers in integrated circuits.
BACKGROUND OF THE INVENTION
When fabricating integrated circuits, layers of insulating, conducting and semiconducting materials are deposited and patterned to produce desired structures. “Back end” or metallization processes include contact formation and metal line or wire formation. Contact formation vertically connects conductive layers through an insulating layer. Conventionally, contact vias or openings are formed in the insulating layer, which typically comprises a form of oxide such as borophosphosilicate glass (BPSG) or an oxide formed from tetraethylorthosilicate (TEOS) precursors. The vias are then filled with conductive material, thereby interconnecting electrical devices and wiring above and below the insulating layers. The layers interconnected by vertical contacts typically include horizontal metal lines running across the integrated circuit. Such lines are conventionally formed by depositing a metal layer over the insulating layer, masking the metal layer in a desired wiring pattern, and etching away metal between the desired wires or conductive lines.
Damascene processing involves forming trenches in the pattern of the desired lines, filling or overfilling the trenches with a metal or other conductive material, and then etching the excess metal back to the insulating layer. Wires are thus left within the trenches, isolated from one another in the desired pattern. The etch back process avoids the more difficult photolithographic mask and etching processes of conventional metal line definition.
In an extension of damascene processing, a process known as dual damascene involves forming two insulating layers, typically separated by an etch stop material, and forming trenches in the upper insulating layer, as described above for damascene processing. After the trenches have been etched, a further mask is employed to etch contact vias downwardly through the floor of the trenches and the lower insulating layer to expose lower conductive elements where contacts are desired.
Conductive elements, such as gate electrodes, capacitors, contacts, runners and wiring layers, must each be electrically isolated from one another for proper integrated circuit operation. In addition to providing insulating layers around such conductive elements, care must be taken to prevent diffusion and spiking of conductive materials through the insulating layers, which can cause undesired short circuits among devices and lines. Protective barriers are often formed between via or trench walls and metals in a substrate assembly to aid in confining deposited material within the via or trench walls. Barriers are thus useful for damascene and dual damascene interconnect applications, particularly for small, fast-diffusing elements such as copper.
Candidate materials for protective barriers should foremost exhibit effective diffusion barrier properties. Additionally, the materials should demonstrate good adhesion with adjacent materials (e.g., oxide via walls, adhesion layers, etch stop layers and/or metallic materials that fill the vias and trenches). For many applications, a barrier layer is positioned in a current flow path and so must be conductive. Typically, barriers have been formed of metal nitrides (MN
x
), such as titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN), which are dense and adequately conductive for lining contact vias, wiring trenches, and other conductive barrier applications.
These lined vias or trenches are then filled with metal by any of a variety of processes, including chemical vapor deposition (CVD), physical vapor deposition (PVD), and electroplating. For effective conductivity and to avoid electromigration during operation, the metal of a contact or wiring layer should fill the via or trench without leaving voids or key holes. Completely filling deep, narrow openings with conductive material is becoming ever more challenging as integrated circuit dimensions are constantly scaled down in pursuit of faster operational processing speeds and lower power consumption.
As illustrated in
FIGS. 1 and 2
, utilizing a conductive barrier layer and/or other liners makes filling the trenches and vias of dual damascene processing even more difficult.
FIG. 1
illustrates a dual damascene process in which an upper insulating layer
10
is formed over a lower insulating layer
12
, which is in turn formed over a conductive wiring layer
14
, preferably with an intervening dielectric diffusion barrier
15
. This dielectric barrier
15
serves to prevent copper or other conductive material of the underlying runner
14
from diffusing into the overlying dielectric layer
12
.
A mask is employed to pattern and etch trenches
16
in a desired wiring pattern. In the illustrated embodiment, the trench
16
is etched down to the level of an etch stop layer
19
, which is formed between the two insulating layers
10
,
12
. This etch stop layer
19
is typically patterned and etched, prior to deposition of the upper insulating layer
10
, to form a hard mask that defines horizontal dimensions of desired contact vias that are to extend from the bottom of the trench
16
. Continued etching through the hard mask
19
opens a contact via
20
from the bottom of the trench
16
to the lower conductive wiring layer
14
.
FIG. 1
also shows an upper etch stop or chemical mechanical polishing (CMP) stop layer
21
over the upper insulating layer
10
to stop a later planarization step, as will be appreciated by the skilled artisan.
Protective liners
22
, preferably formed of conductive material, are then formed on the exposed horizontal and sidewall surfaces. Typically, the liners
22
at least include a metal nitride, and may additionally include adhesion enhancing and seeding layers. For example, the liner
22
can comprise a tri-layer of Ti/TiN/Cu. In such a structure, the titanium layer serves to improve adhesion with exposed oxide sidewalls; the titanium nitride serves as a diffusion barrier; and a thin copper layer serves as a seed for later electroplating of copper. In other examples, the liners
22
can include tantalum nitride or tungsten nitride barriers. The skilled artisan will appreciate that other barrier materials can also be employed.
Conformal deposition of the liners
22
, however, is very difficult with conventional processing. For example, physical vapor deposition (PVD), such as sputtering, of a metal layer (for adhesion, barrier and/or seed layer) requires at least about 50 Å over all surfaces of the trench
16
and contact via
20
. Unfortunately, PVD of metal into high aspect ratio voids necessitates much greater deposition on the top surfaces of the workpiece to produce adequate coverage of the via bottom. For example, typical state-of-the-art trench and contact structures for dual damascene schemes require about 500 Å PVD metal in order for 50 Å of metal to reach the bottom and sidewalls of the contact via
20
.
This poor step coverage is a result of the high aspect ratio of voids formed for dual damascene processing in today's integrated circuit designs. The aspect ratio of a contact via is defined as the ratio of depth or height to width. In the case of dual damascene contacts, the trench
16
and contact via
20
together reach through two levels of insulating layers
10
,
12
, such that the effective aspect ratio of the via
20
is very high.
Conventional deposition processes produce very poor step coverage (i.e., the ratio of sidewall coverage to field or horizontal surface coverage) of such high aspect ratio vias for a variety of reasons. Due to the directionality of PVD techniques, for example, deposition tends to accumulate more rapidly at upper corners
26
of the trench
16
and upper corners
28
of the via
20
, as compared to the via bottom
3

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