Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Gettering of semiconductor substrate
Reexamination Certificate
2005-10-25
2005-10-25
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Gettering of semiconductor substrate
C438S310000, C438S311000, C438S402000, C438S471000, C438S473000, C438S517000
Reexamination Certificate
active
06958264
ABSTRACT:
A method of manufacturing a semiconductor device on a silicon-on-insulator wafer including a silicon active layer having at least two die pads formed thereon, the at least two die pads separated by at least one scribe lane, including the steps of forming at least one cavity through the silicon active layer in the at least one scribe lane; forming at least one gettering plug in each said cavity, each said gettering plug comprising doped fill material containing a plurality of gettering sites; and subjecting the wafer to conditions to getter at least one impurity into the plurality of gettering sites. A silicon-on-insulator semiconductor wafer including a silicon active layer; a plurality of die pads formed in the silicon active layer; at least one scribe lane between and separating adjacent die pads; and at least one gettering plug in the at least one scribe lane, wherein the at least one gettering plug extends through the silicon active layer and the gettering plug comprises a doped fill material having a plurality of gettering sites.
REFERENCES:
patent: 3936858 (1976-02-01), Seeds et al.
patent: 4371403 (1983-02-01), Ikubo et al.
patent: 4498227 (1985-02-01), Howell et al.
patent: 4589928 (1986-05-01), Dalton et al.
patent: 5162241 (1992-11-01), Mori et al.
patent: 5194395 (1993-03-01), Wada
patent: 5244819 (1993-09-01), Yue
patent: 5272104 (1993-12-01), Schrantz et al.
patent: 5443661 (1995-08-01), Oguro et al.
patent: 5453153 (1995-09-01), Fan et al.
patent: 5453385 (1995-09-01), Shinji
patent: 5501993 (1996-03-01), Borland
patent: 5616513 (1997-04-01), Shepard
patent: 5646053 (1997-07-01), Schepis et al.
patent: 5677222 (1997-10-01), Tseng
patent: 5892292 (1999-04-01), Easter
patent: 6001711 (1999-12-01), Hashimoto
patent: 6228748 (2001-05-01), Anderson et al.
patent: 6252294 (2001-06-01), Hattori et al.
patent: 6271541 (2001-08-01), Yamaguchi et al.
patent: 6274460 (2001-08-01), Delgado et al.
patent: 6352924 (2002-03-01), Wu et al.
patent: 6383914 (2002-05-01), Yasuda
patent: 6444534 (2002-09-01), Maszara
patent: 6465873 (2002-10-01), Gonzalez
patent: 6509248 (2003-01-01), Gonzalez
patent: 6551866 (2003-04-01), Maeda
patent: 6555457 (2003-04-01), Derkits et al.
patent: 6586295 (2003-07-01), Ohno
patent: 2001/0004543 (2001-06-01), Moore
patent: 63-271941 (1988-09-01), None
patent: 2000-323484 (2000-11-01), None
patent: 99/26291 (1999-05-01), None
Wolf et al.; “Silicon Processing for the VLSI Era”; Crystalline Defects, Thermal Processing and Gettering; Basic Gettering Principles; vol. 1: Process Technology; pp. 63-70.
Dziesiatv et al.; Improved SI-EPI-Wafers by Buried Damage Layer for Extrinsic Gettering; pp. 292-296.
IBM Technical Disclosure Bulletin; Gettering Technique and Structure; May 1975.
Wong et al.; “Nanoscale CMOS”; Proceedings of the IEE, vol. 87, No. 4; Apr. 1999; pp. 537-570.
Coleman W. David
Nguyen Khiem
Renner , Otto, Boisselle & Sklar, LLP
LandOfFree
Scribe lane for gettering of contaminants on SOI wafers and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Scribe lane for gettering of contaminants on SOI wafers and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scribe lane for gettering of contaminants on SOI wafers and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3452205