Scheme for eliminating the effects of duty cycle asymmetry...

Details Scheme for eliminating the effects of duty cycle asymmetry... Scheme for eliminating the effects of duty cycle asymmetry...

2007-10-30

2007-10-30

Lamarre, Guy (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error detection for synchronization control

C714S707000, C714S034000, C713S500000

Reexamination Certificate

active

10706813

ABSTRACT:
A clock management system receives an input clock signal having rising edges and falling edges, a first set of data values associated with the rising edges of the input clock signal, and a second set of data values associated with the falling edges of the input clock signal. The clock management system provides a first clock and a second clock in response to the input clock signal. The first clock has a first set of edges that are synchronous with the rising edges of the input clock signal. The second clock has a second set of edges that are synchronous with the falling edges of the input clock signal. The first set of data values are latched in response to the first set of edges of the first clock. The second set of data values are latched in response to the second set of edges of the second clock.

REFERENCES:
patent: 5881271 (1999-03-01), Williams
patent: 6049883 (2000-04-01), Tjandrasuwita
patent: 7034596 (2006-04-01), Andrews et al.
patent: 2004/0243874 (2004-12-01), Byers et al.
Xilinx, Inc., “Logicore,” Sp1-4.2 Core v6.0.1, Product Specification DS209, Oct. 10, 2003, pp. 1-97, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Xilinx, Inc., “644-MHz SDR LVDS Transmitter/Receiver,” Application Note: Virtex-II Series, XAPP622, Nov. 5, 2003, v1.5, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Rhodes, Martin; “XGMII Using the DDR Registers, DCM and Selectl/O-Ultra Features”, XAPP606, Jul. 10, 2002, pp. 1-11, v1.1, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.

Affiliated with

Also associated with

Rating

Scheme for eliminating the effects of duty cycle asymmetry... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scheme for eliminating the effects of duty cycle asymmetry..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scheme for eliminating the effects of duty cycle asymmetry... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3892751