Scannable dynamic logic latch circuit

Details Scannable dynamic logic latch circuit Scannable dynamic logic latch circuit

2006-10-31

2008-05-13

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S093000, C326S095000

Reexamination Certificate

active

07372305

ABSTRACT:
A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch output and to the dynamic node of the dynamic logic gate. A scan clock and a normal clock determine whether the logic circuitry is in the normal logic mode or in the scan test mode. A static output latch has at least one input that is responsive logic state of a dynamic node. The evaluated state of the dynamic node is set by either the logic tree of the dynamic logic gate or the scan pull-down logic tree of the scan circuitry in response to the logic state of the scan clock or the normal clock.

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