Scan of chip state from a hierarchical design

Details Scan of chip state from a hierarchical design Scan of chip state from a hierarchical design

2006-12-26

2006-12-26

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S729000

Reexamination Certificate

active

07155647

ABSTRACT:
A method and mechanism for observation, testing, and diagnosis with scan chains. A device under test is configured to support scan chains. The device includes multiple blocks, each of which are configured to be individually tested with separate scan chains. Each block is configured to recirculate the scan output of its block back into its scan chain during the cycles in which it is not being directly scanned out of the chip. As the scan clock is pulsed N cycles and another block of the chip is scanned out, the recirculated state of the block will shift within the block N positions. By keeping track of the scan chain lengths of each of the blocks in the chip, and the order in which they are scanned, a determination may be made as to which element of the scan chain will be shifted out of the next block to be scanned. Further, by knowing the length N of the scan chain of a particular block and the number of cycles M it has been recirculated, the scan chain may be shifted (M % N) cycles to return the block to its originally ordered state before scanning it out.

REFERENCES:
patent: 5717702 (1998-02-01), Stokes et al.
patent: 6028983 (2000-02-01), Jaber
patent: 6530052 (2003-03-01), Khou et al.
patent: 6779143 (2004-08-01), Grisenthwaite

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