Scan latch circuit

Details Scan latch circuit Scan latch circuit

2000-04-11

2003-09-16

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000

Reexamination Certificate

active

06622273

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a scan latch circuit useable where alternative testing methods are employed on an associated circuit, and to the combination of such a scan latch circuit with an associated circuit.
BACKGROUND OF THE INVENTION
Scan latches are known components of test circuitry for circuits, and especially complex circuits such as memories. Such scan lathes typically have a two-input multiplexer with a control input for selecting between those two inputs from the output of the multiplexer feeding to latch circuitry. The control input receives a two state signal called scan enable, so that when it is a logical 1 state the second input, the scan input is applied from the multiplexer output to the latch circuitry. When the scan enable input is at logical 0, the first input, the data input is provided by the multiplexer to the latch circuitry.
Where such scan latches are used with a built-in self-test (BIST) arrangement—so that both scan test and built-in self-test (BIST) can be used—it is conventional to connect an input multiplexer to the first input of the scan latch, the input multiplexer having a first input for data output from the memory, a second input for the built-in self-test data from the memory and a control input for selecting between the two inputs.
Such a scan latch circuit is disadvantageous in that an additional gate delay is built in to the memory data path.
It is accordingly an object of the present invention to overcome difficulties of the prior art.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided a scan latch circuit for a circuit having a data output and first and second outputs for test information, the scan latch circuit comprising a scan latch having first and second inputs and a control input for selecting between said first and second inputs for input to latch circuitry of said scan latch, the circuit further having first and second select signal inputs for selecting first and second test modes in which a respective one of said first and second test information is passed to said latch circuitry, wherein said data output is connected directly to one of said first and second inputs of said scan latch, and wherein said first and second outputs and said first and second select signals are connected by further circuitry to said control and said other input of said scan latch.
Preferably said further circuitry comprises a two input multiplexer having one input connected to receive said first output, the other input of said two input multiplexer being connected to receive said second output, the select terminal of said multiplexer being connected to receive one of said first and second select signals.
Advantageously said first and second select signals are connected to the control input of said scan latch via an OR gate whereby said control input responds to the logical OR of said select signals.
According to a second aspect of the invention there is provided the combination of a scan latch circuit and a circuit having a data output and first and second outputs for test information, the scan latch circuit comprising a scan latch having first and second inputs and a control input for selecting between said first and second inputs for input to latch circuitry of said scan latch, the scan latch circuit further having first and second select signal inputs for selecting first and second test modes in which a respective one of said first and second test information is passed to said latch circuitry, wherein said data output is connected directly to one of said first and second inputs of said scan latch, and wherein said first and second outputs and said first and second select signals are connected by further circuitry to said control and said other input of said scan latch.
According to a third aspect of the invention there is provided the combination of a scan latch circuit and a memory having a data output and first and second outputs for test information, the scan latch circuit comprising a scan latch having first and second inputs and a control input for selecting between said first and second inputs for input to latch circuitry of said scan latch, the scan latch circuit further having first and second select signal inputs for selecting first and second test modes in which a respective one of said first and second test information is passed to said latch circuitry, wherein said data output is connected directly to one of said first and second inputs of said scan latch, and wherein said first and second outputs and said first and second select signals are connected by further circuitry to said control and said other input of said scan latch.
Preferably said further circuitry comprises a two input multiplexer having one input connected to receive said first output, the other input of said two input multiplexer being connected to receive said second output, the select terminal of said multiplexer being connected to receive one of said first and second select signals.
Advantageously said first and second select signals are connected to the control input of said scan latch via an OR gate whereby said control input responds to the logical OR of said select signals.
Conveniently said circuit comprise a memory.


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patent: 6158032 (2000-12-01), Currier et al.
patent: 6185710 (2001-02-01), Barnhart
patent: 6195775 (2001-02-01), Douskey et al.
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patent: 0 822 497 (1998-02-01), None
European Standard Search Report from GB 9920077, filed Aug. 24, 1999.

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