Scan flop circuitry and methods for making the same

Details Scan flop circuitry and methods for making the same Scan flop circuitry and methods for making the same

1999-05-21

2002-05-21

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S729000

Reexamination Certificate

active

06393592

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated circuits (ICs) and more particularly concerns integrated scan flop cells that can be used to facilitate scan testing of integrated circuit designs.
2. Description of the Related Art
In an effort to remain competitive in the marketplace, chip manufacturers are constantly striving to optimize the design and efficiency of their ICs by increasing chip speed, quality and the density of internal circuit components. Commensurate with meeting these objectives is to maximize fault coverage when testing their IC designs. A common industry design practice is to make the IC design scannable by implementing scan cells. Among many types of scan cells, the most common one is the so called “muxed-scan,” or also referred to herein as a “scan flop.”
FIG. 1A
illustrates a conventional scan flop
100
having a multiplexer
102
and a D flip flop
104
. Generally, the scan flop
100
has a system data input (DI) and a scan data input (SI) that are respectively connected to the multiplexer
102
. The muliplexer
102
is configured to receive a scan enable (SE) and output a signal to a D input of the D flip-flop
104
. The scan flop
100
also receives a clock signal (CP) which is communicated to the D flip-flop
104
, and output pins Q and NQ that are also selectively output from the D flip-flop
104
. The scan flop is therefore configured to operate in one of two modes. The first mode is a “system” mode (also known as the functional mode), and the second mode is a “scan” mode (also known as the test mode).
Figure 1B
illustrates a simplified semiconductor chip
101
having a scan chain that is made up of a plurality of interconnected scan flops
100
. In actuality, when a full-scan design is implemented for a semiconductor chip
101
, many more scan chains are integrated into the IC design to enable the scan test to achieve the highest fault coverage. However, for this simplified example, the first scan flop
100
of the scan chain has its scan data input (SI) connected to a pad
110
, and a pad
112
connected to the output pin Q of the last scan flop
100
. Also shown is a clock (CLK) pad connected to each of the clock signals (CP) of the individual scan flops
100
. The output pins Q of each of the scan flops
100
of the scan chain are shown connected to the scan data inputs (SI). In this common scan chain design, non-scan chain logic
106
is also connected to the output pins Q and the scan data inputs (SI).
Additionally, non-scan chain logic
106
may further be connected to the output pins NQ. When the scan flop
100
is in the functional system mode, the scan enable (SE) signal is constrained to ground, such that the scan flop
100
operates identically to the D flip-flop
104
. In the scan mode, the scan enable (SE) signal is active high in shifting.
To properly implement scan on a chip, the chip would have to be synchronous by design. Thus, designs that have more than one clock domain are generally difficult to test using chains of scan flops. Thus, most if not all scan flops would have to be clocked by one of the few main clock signals that run throughout the chip. Accordingly, for chips that do not meet this criteria, either by design or necessity, a regular scan approach would not be possible.
An attempt to solve this problem includes using level-sensitive scan device (LSSD) methods. LSSD was originally designed by inserting scan into latches. The edge trigger flop derived LSSD, however, still required two non-overlapping clocks. Not only does it take additional logic to generate two non-inverting clocks, it also takes up more routing area on a chip.
In addition, scan flops with asynchronous set and/or reset will also need to have these ports blocked because of their asynchronous nature. This, unfortunately, lowers the fault coverage on the nodes that control these pins. If the asynchronous set and/or reset is not blocked during scan mode operations (e.g., shifting), an asynchronous reset can inadvertently trigger a reset and clear the result that is to be shifted out. More specifically, the cloud of logic that drives the asynchronous reset (and which is not controlled by a scan pin), can cause the test pattern to be cleared. When this happens, the test tool will not be able to shift the test pattern through, and as a result the testing will not work.
In view of the foregoing, there is a need for integrated scan circuitry that can handle multiple clock domains without increasing external circuit complexity. There is also need for integrated scan circuitry that can protect scan flops from inadvertent sets and resets during scan mode testing.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing scan flop circuitry for handling multiple clock domains. The scan flop circuitry of the present invention can also be integrated with logic that internally converts asynchronous set/reset conditions into synchronous set/reset conditions during scan mode operations. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a scan flop cell is disclosed. The scan flop cell includes a D flip-flop, a scan multiplexer, and a clock multiplexer. The clock multiplexer is configured to receive a functional clock and a scan clock, and a scan mode terminal SM controls the output of the clock multiplexer. The scan flop cell also preferably includes a data terminal D, a scan input terminal SI, a scan enable terminal SE, a functional clock terminal C, a scan clock terminal SC, and the scan mode terminal SM.
In this embodiment, the scan flop cell can also include asynchronous reset blocking circuitry. The asynchronous reset blocking circuitry includes: (a) a multiplexer that is connected to an output of the scan multiplexer and to the data terminal D, and the multiplexer has an output that connects to a data node of the D flip-flop; (b) an OR gate having an input connected to the data terminal D and another input connected to an output of an inverter; an input of the inverter is connected to an NS terminal of the scan flop cell, and an output of the OR gate that connects to the scan multiplexer; and (c) an OR gate having one input connected to the scan mode terminal and another input connected to the NS terminal, and an output of the OR gate that is coupled to a set terminal of the D flip flop.
Still in this embodiment, the scan flop can include asynchronous set blocking circuitry. The asynchronous set blocking circuitry includes: (a) a multiplexer that is connected to an output of the scan multiplexer and to the data terminal D, and the multiplexer has an output that connects to a data node of the D flip-flop; (b) an OR gate having an input connected to the data terminal D and another input connected to an output of an inverter; an input of the inverter is connected to an NS terminal of the scan flop cell, and an output of the OR gate connects to the scan multiplexer; (c) and an OR gate having one input connected to the scan mode terminal and another input connected to the NS terminal, and an output of the OR gate is coupled to a set terminal of the D flip flop.
In another embodiment, an integrated scan flop circuit is disclosed. The integrated scan flop circuit includes a D flip-flop circuit, a scan multiplexer, another multiplexer, a clock multiplexer; an asynchronous set blocking OR gate that has an output connected to a set terminal of the D flip-flop, and an asynchronous reset blocking OR gate that has an output connected to a reset terminal of the D flip flop. In this embodiment, the scan flop can be implemented for conditions in which either the scan flop is set dominant or for conditions in which the scan flop is reset dominant.
In yet another embodiment, a method for making scan flop cell for use in scan testing an integrated circuit design is disclosed. The metho

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